/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design-season-2---post-17Multichannel and Overclocking FIRs - The Single Rate Symmetric Case In the last post I created an overclocked or semi-parallel implementation of a systolic, non-symmetric FIR, where each DSP48 in the chain implements M taps of the filter. ...en-USTelligent Community 12