<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Avnet HDL git HOWTO (Vivado 2020.2 and later)</title><link>/technologies/fpga-group/b/blog/posts/avnet-hdl-git-howto-vivado-2020-2-and-later</link><description>This is an update to the popular Avnet HDL git HOWTO (Vivado 2020.1 and earlier) blog post. You may know that Avnet provides PetaLinux BSPs and other reference designs for the Xilinx Zynq and Zynq UltraScale+ Zed SOMs (MicroZed, PicoZed, and Ult...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Avnet HDL git HOWTO (Vivado 2020.2 and later)</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/avnet-hdl-git-howto-vivado-2020-2-and-later</link><pubDate>Fri, 15 Mar 2024 23:56:42 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1ff2d85a-c735-4184-b428-f24d2d05b7f3</guid><dc:creator>dyessgg</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Unfortunately, many of those are outdated and some Avnet boards are dropped altogether.&amp;nbsp; My UltraZED v1 board has NEVER been supported well.&amp;nbsp; My UltraZED-3EG board stopped being supported well since 2021.&amp;nbsp; The 2023 has several old bits that simply will not build.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=11206&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Avnet HDL git HOWTO (Vivado 2020.2 and later)</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/avnet-hdl-git-howto-vivado-2020-2-and-later</link><pubDate>Mon, 11 Mar 2024 16:44:03 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1ff2d85a-c735-4184-b428-f24d2d05b7f3</guid><dc:creator>nbaldy5</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Well, this is frustrating.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;It&amp;#39;s not compatible with the version of vivado which took me quite a while to install, and I have to downgrade. This writeup is great, but it&amp;#39;s hard not to get frustrated by the constant spinning in circles which occurs from the lackluster official documentation and linkage of these boards and software requirements. How do engineers more experienced than me approach these problems? Is it just a good idea to install older versions of these tools? What&amp;#39;s the upgrade plan, if any? Should I just assume I should freeze all of my tools and installs at 2020.2? What about if a newer board comes out? Are most engineers running these tools within docker containers for running multiple versions?&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=11206&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Avnet HDL git HOWTO (Vivado 2020.2 and later)</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/avnet-hdl-git-howto-vivado-2020-2-and-later</link><pubDate>Fri, 23 Jun 2023 15:31:44 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1ff2d85a-c735-4184-b428-f24d2d05b7f3</guid><dc:creator>dyessgg</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;VERY nice!&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Questions:&lt;/p&gt;
&lt;p&gt;1. The most current is for Vivado 2022.2.&amp;nbsp;&amp;nbsp;&lt;span&gt;Any idea when 2023.1 will be included?&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;2. Is there documentation on how to use the additional reference examples?&amp;nbsp; I&amp;#39;m quite interested in the HDMI out on UZ3 boards.&lt;/span&gt;&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=11206&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Avnet HDL git HOWTO (Vivado 2020.2 and later)</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/avnet-hdl-git-howto-vivado-2020-2-and-later</link><pubDate>Wed, 11 Aug 2021 17:21:49 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1ff2d85a-c735-4184-b428-f24d2d05b7f3</guid><dc:creator>bigguiness</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;I&amp;#39;m trying to use the git repositories to build a setup for a Minized board using the 2020.2 tools.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;When I run the ~/git/avnet/petalinux/scripts/make_minized_sbc_base.sh script I get the following:&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;&lt;span&gt;&lt;span&gt;Patching PetaLinux project config ... &lt;/span&gt;&lt;br /&gt; &lt;br /&gt; &lt;br /&gt;Tag 2020p2_minized_sbc_20210426_105325 not found.&amp;nbsp; Cloning 2020.2 branch instead. &lt;br /&gt; &lt;br /&gt; &lt;br /&gt;***WARNING:&amp;nbsp; This may result in build mismatch!***&lt;br /&gt;&lt;/span&gt;&lt;/p&gt;&lt;p&gt;&lt;span&gt; &lt;/span&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Is this expected? If not is there a way to fix it?&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Thanks&lt;/p&gt;&lt;p&gt;&lt;span&gt; &lt;/span&gt;&amp;nbsp;&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=11206&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Avnet HDL git HOWTO (Vivado 2020.2 and later)</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/avnet-hdl-git-howto-vivado-2020-2-and-later</link><pubDate>Mon, 10 May 2021 15:23:31 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1ff2d85a-c735-4184-b428-f24d2d05b7f3</guid><dc:creator>bhfletcher</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Does E14 have the ability to attach a higher resolution image? I wanted to zoom in on that completed Block Diagram above. I see a bunch of repeated blocks in the upper right and lower right. I believe those are related to another post where &lt;span&gt;[mention:d9bbdf0c884948d98adeddd926e50709:e9ed411860ed4f2ba0265705b8793d05]&lt;/span&gt; pointed out that those were unused reset and clock placeholders to allow for future Accelerator connections in Vitis AI, but I was hoping to confirm.&lt;/p&gt;&lt;p&gt;Bryan&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=11206&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Avnet HDL git HOWTO (Vivado 2020.2 and later)</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/avnet-hdl-git-howto-vivado-2020-2-and-later</link><pubDate>Thu, 29 Apr 2021 15:50:48 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1ff2d85a-c735-4184-b428-f24d2d05b7f3</guid><dc:creator>drozwood90</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Great writeup Tom!&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=11206&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>