Learning Xilinx Zynq: use AXI with a VHDL example in Pynq/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-axi-with-a-vhdl-example-in-pynqThe goal of this blog series is to master the Xilinx Zynq. I&#39;m using the PWM design of my previous post and switch to AXI memory map interface between ARM and FPGA. I learned this from beacon_dave &#39;s PYNQ-Z2 Workshop - AXI GPIO post. &amp;...en-USTelligent Community 12RE: Learning Xilinx Zynq: use AXI with a VHDL example in Pynqhttps://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-axi-with-a-vhdl-example-in-pynqSat, 19 Jun 2021 17:25:05 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:836e77d6-5ad2-46e8-8e0e-c61d65614638Jan Cumps1<p>I&#39;m now going through the workshops. It&#39;s similar to what&#39;s been presented on the element14 webinars: <a class="jive-link-event" href="https://www.element14.com/community/events/5307/l/unlock-the-power-of-fpgas-through-python-building-reconfigurable-embedded-systems-with-pynq">Unlock the Power of FPGAs through Python: Building Reconfigurable Embedded Systems with PYNQ</a></p><p>&nbsp;</p><p>The documents, examples and bitstreams are on GIT. To make them available and executable from the Pynq board, I used this set of commands, executed from the Jupyter terminal window (suggestion: change user to xilinx by executing su xilinx):</p><p>&nbsp;</p><p>[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=text&amp;text=mkdir+%2Fhome%2Fxilinx%2Fpynq_workshop%0Acd+%2Fhome%2Fxilinx%2Fpynq_workshop%0Agit+clone+https%3A%2F%2Fgithub.com%2FXilinx%2FPYNQ_Workshop.git%0Aln+-s+%2Fhome%2Fxilinx%2Fpynq_workshop%2FPYNQ_Workshop+%2Fhome%2Fxilinx%2Fjupyter_notebooks%2FPYNQ_Workshop]</p><div></div><p>&nbsp;</p><p>It keeps the workshop files separate from any other software, but integrates it with the Jupyter notebook:</p><p><span>[View:/resized-image/__size/620x311/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-836e77d6-5ad2-46e8-8e0e-c61d65614638/8053.contentimage_5F00_208428.png:620:311]</span></p><p>&nbsp;</p><p>Action photo:</p><p><span>[View:/resized-image/__size/620x662/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-836e77d6-5ad2-46e8-8e0e-c61d65614638/7457.contentimage_5F00_208429.png:620:662]</span></p><p>How to get at the terminal:</p><p><span>[View:/resized-image/__size/620x185/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-836e77d6-5ad2-46e8-8e0e-c61d65614638/1680.contentimage_5F00_208430.png:620:185]</span></p><p>&nbsp;</p><p>&nbsp;</p><p>That&#39;s it. A small set of 4 commands to get started.</p><img src="https://community.element14.com/aggbug?PostID=11499&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">RE: Learning Xilinx Zynq: use AXI with a VHDL example in Pynqhttps://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-axi-with-a-vhdl-example-in-pynqThu, 10 Jun 2021 22:34:51 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:836e77d6-5ad2-46e8-8e0e-c61d65614638Jan Cumps1<p>fun addon:</p><p>&nbsp;</p><p>[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=python&amp;text=from+time+import+sleep%0Atry%3A%0A++++while+True%3A%0A++++++++for+i+in+range+%280%2C+255%29%3A%0A++++++++++++pwm_register%5B0%3A8%5D.write%28i%29%0A++++++++++++sleep%280.005%29%0Aexcept+KeyboardInterrupt%3A%0A++++pass]</p><div></div><p>&nbsp;</p><p>&nbsp;</p><p><span>[View:/resized-image/__size/270x462/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-836e77d6-5ad2-46e8-8e0e-c61d65614638/contentimage_5F00_208427.gif:270:462]</span></p><img src="https://community.element14.com/aggbug?PostID=11499&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">