VHDL PWM generator with dead time: the design

RE: VHDL PWM generator with dead time: the design

wolfgangfriedrich — Mon, 21 Jun 2021 15:46:01 GMT

Overall a great example how simple it is to implement functionality in VHDL.

2 things I would like to mention to make it even better.

1) The module is missing a reset signal, to make it start at a defined state.

Something like this (updated lines 3,17,18,19:

entity Pwm is
port (
n_reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- Input clock.
duty_i : in std_logic_vector (7 downto 0); -- Duty-cycle input.
band_i : in std_logic_vector (3 downto 0); -- number of clock-ticks to keep both signals low before rising edge
pwmA_o : out std_logic; -- PWM output.
pwmB_o : out std_logic -- PWM output inverse.
);
end entity;
architecture arch of Pwm is
signal timer_r : natural range 0 to 2**duty_i'length-1;
begin
process(clk_i)
begin
if n_reset_i = '0' then
timer <= 0;
elsif rising_edge(clk_i) then

2) It is good practice to have output signals of a module synchronous to its clock and not being straight from combinatorial logic.

The first attempt "Full VHDL" had all logic description encased by the 'if (rising_edge(clk_i)', which generates flipflops for each signal.

The latest version (in the comments) has only the timer_r sync to the input clock and the outputs are generated from logic only.

This can cause timing issues when you use those signals for more logic operations outside the module before going through the next register.

I hope this makes sense.

- W.

RE: VHDL PWM generator with dead time: the design

jc2048 — Sun, 20 Jun 2021 17:00:53 GMT

I should probably stop doing this, but here's one more for luck. This is on a VIDOR 4000 (a Cyclone 10 FPGA).

[View:/resized-image/__size/620x349/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-19e2b967-6da5-4f5f-adb0-9122e09ee76d/0116.contentimage_5F00_208435.png:620:349]

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[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-19e2b967-6da5-4f5f-adb0-9122e09ee76d/2063.contentimage_5F00_208437.png:480:234]

RE: VHDL PWM generator with dead time: the design

Jan Cumps — Thu, 17 Jun 2021 17:37:17 GMT

The Zynq approach is interesting. I didn't have a clue when I got the board.

I knew it was a processor and FPGA combination on a single chip. But sceptic on the value of that.

I thought that the Linux part would distract from the FPGA part. After working with the board, I realised that isn't true.

There is (maybe unintended) value when learning VHDL/Verilog: It's easier to create test beds for the custom bitstreams you are creating.

You can make a small component or large design. The Linux / Pynq combination allow to put that code to test fairly easy.

It took me a day to learn that, and I have a higher learning speed since that.

Part of that are the Jupyter books. They make it easy to write test scenarios and run them repeatedly.

The real "in production" value is that there is a close integration between the ARM processors and FPGA fabric.

I didn't understand it after reading product overviews. I needed a hands-on to see it.

I can see these immediate values:

you can write hardware designs that act as common peripherals. You control them from Linux via memory mapped register locations. Supports hardware interrupts.
Data steams both ways (with DMA!): an efficient stream between Linux and your FPGA designs
Speed up an application: implement algorithms in the FPGA - this is exciting: it's possible to write C algorithms and convert them into FPGA designs.
If your algorithm is processor-expensive and a candidate for this, you can speed up functions by executing them in hardware instead of CPU.
There are examples of real time encryption/decryption and image processing.
Works for intensive algorithms that don't need OS functionality (file access, ...)

RE: VHDL PWM generator with dead time: the design

jc2048 — Thu, 17 Jun 2021 13:41:11 GMT

VHDL is fairly portable at the level of the basic programmable logic. Here is Jan's code moved to an Intel (Altera) device, a Max II CPLD (EPM240T100C5N). It's very much less capable than the Xilinx part, with only 240 logic elements, but there's enough room for something simple like this. Not having an inbuilt processor and not wanting to spend the time wiring up a real microcontroller to the CPLD, I cheated and set the duty and deadband to be fixed constants: not very useful in a real system, but fine for the illustration.

Here's the Quartus Lite screen after it had compiled successsfully

[View:/resized-image/__size/620x349/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-19e2b967-6da5-4f5f-adb0-9122e09ee76d/6131.contentimage_5F00_208432.png:620:349]

here's the board with the probes attached

[View:/resized-image/__size/600x450/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-19e2b967-6da5-4f5f-adb0-9122e09ee76d/4087.contentimage_5F00_208433.jpg:600:450]

and here are the waveforms that are produced

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-19e2b967-6da5-4f5f-adb0-9122e09ee76d/7120.contentimage_5F00_208434.png:480:234]

RE: VHDL PWM generator with dead time: the design

cstanton — Mon, 14 Jun 2021 14:39:54 GMT

For some reason I thought the code would look more obscure than it does...

RE: VHDL PWM generator with dead time: the design

genebren — Sun, 13 Jun 2021 19:33:16 GMT

Great PWM example code.