<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Learning Xilinx Zynq: use AXI and MMIO with a VHDL example in Pynq</title><link>/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-axi-and-mmio-with-a-vhdl-example-in-pynq</link><description>The goal of this blog series is to master the Xilinx Zynq.
I&amp;#39;m using the PWM design of my previous posts , and now switch to the raw AXI memory map interface between ARM and FPGA.
In the previous post, I used AXI GPIO , the first step to memory map..</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>