Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control

RE: Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control

Jan Cumps — Thu, 20 Apr 2023 19:52:06 GMT

It's been so long ago that I completely forgot how Pynq and Jupiter work. Reading my own post [mention:b372f53a71cb44769f65ea935e407b8b:f7d226abd59f475c9d224a79e3f0ec07]

RE: Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control

yepe — Thu, 20 Apr 2023 06:55:03 GMT

Hi Jan Cumps, I hope you don't mind if I ask a question regarding the PYNQ half-bridge PWM driver. I am working on a student project for school and I need to drive a half-bridge for an ultrasound pulser. I was working through your great tutorial and I had the complementary pwm output on my board PYNQ Z1. However, I have to make certain changes to the operation to make it compatible with my needs which I attempted to do, but I could not determine the best approach. First off, I need to simplify that I only need 50% duty cycle and no other duty cycles needed. I have made a timing diagram for the various waveforms:

CLK should be a continuous 20 MHz signal, PRF should be a 10 kHz 50% duty cycle signal that synchronizes the rest of the waveforms. PWM&PWMN are the complementary PWM signals with dead-time of programmable N cycles with a timed delay from a falling edge of PRF. PULSE should be equal to the length of the PWM pulse train, and GATE is equal to pulse but with a programmable delay. The PWM pulse-train should be 5 MHz. The first thing I tried to do is to change your example to see if I could get a 5 MHz complementary PWM but I could not see how the frequency is determined so I was playing around with the board clocks and only could get it up to 650 kHz.

I am a biginner at vhdl so I am a bit out of my element. I have developed all the electronics and analogue demodulation circuits but I still lack the control system to tie it together. If I were to implement these signals in the PYNQ, where do you propose to start?

RE: Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control

Jan Cumps — Fri, 13 Aug 2021 12:01:18 GMT

I've added a second video, with the FPGA PWM actually driving a home-made GaN half bridge.

[View:https://www.youtube.com/watch?v=WH33_7QTxrY:740:466]

RE: Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control

Jan Cumps — Sat, 10 Jul 2021 13:55:44 GMT

I've been looking at other people's AXI (memory map) implementation, and I see I have an error in all my AXI designs:

I connected the processor's interconnect_axi reset to all my resets, but it is only intended for the AXI input of the AXI Interconnect IP.

For other blocks, I'd have to use peripheral_reset. This reset triggers at the same time, waits 16 clocks more before release.

I've updated my model. I'll zip the example and re-upload ...

[View:/resized-image/__size/620x283/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-ddb4865e-0d80-4c18-8f46-d0c010744131/4774.contentimage_5F00_208445.png:620:283]