RE: VIDOR 4000: Clock Jitter

Jan Cumps — Wed, 14 Jul 2021 23:40:23 GMT

In the Zync 7 that I'm working with the last month, the clocks for the fpga fabric are generated by PLL modules (I would not call them peripherals because they are not external facing) in the ARM part of the silicon.

I haven't checked the specs yet.

RE: VIDOR 4000: Clock Jitter

michaelkellett — Tue, 13 Jul 2021 08:56:56 GMT

I'm not that suprised that the SAM output clock is jittery - where does it get its clock input from ?

People often use differential clock inputs on modern fast FPGAs.

Not sure that the Cyclone 10 quite counts as a modern fast FPGA but it probably deserves a better clock - putting a better clock off board and through connectors might not be that much of an improvement.