VIDOR 4000: Servo Interface

RE: VIDOR 4000: Servo Interface

jc2048 — Mon, 02 Aug 2021 11:46:33 GMT

Mine works with a servo, too. This is 15 degree steps from -60 to +60, and then go back and start again.

[View:https://players.brightcove.net/1362235890001/NkxiVJdjx_default/index.html?videoId=6266222611001:740:466]

But as [mention:b0bc65b9ecdc4307bd967592f00e340a:e9ed411860ed4f2ba0265705b8793d05] predicted, the timing is out. The last step is missing and the one prior to that is a short one, so the limit at that end of the travel is a good bit lower than the 'standard' 2000us I was working to.

RE: VIDOR 4000: Servo Interface

Jan Cumps — Sat, 31 Jul 2021 10:46:44 GMT

The design works. Tested with an Sparkfun micro servo.

[View:https://www.youtube.com/watch?v=SC4h4herhw8:370:240]

I think that servo is the same as the blue ones you use, just older black housing.

RE: VIDOR 4000: Servo Interface

Andrew J — Sat, 31 Jul 2021 06:36:54 GMT

Very interesting. The back-and-forth discussions on these (types of) posts give some really useful insights on considerations and what to check for.

RE: VIDOR 4000: Servo Interface

Jan Cumps — Fri, 30 Jul 2021 20:12:17 GMT

I'm trying to implement your design on the Zynq.

The only change I make is the interface.

Because the processor and the FPGA are on the same silicon, an internal memory mapped register (shared between ARM part and FPGA fabric) makes more sense than an external SPI.

I kept the same format: 16 bits wide, with 3 bits to select the servo and 8 to set the angle. The remaining MSBs ignored.

But I get them in bulk. Not bit per bit from the SPI data pin.

To reflect that, I renamed the received data register from spi_shift_register to data_register.

[View:/resized-image/__size/620x323/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-bb451b64-fed0-4c16-9f62-2a8c67a9ed53/4503.contentimage_5F00_208368.png:620:323]

VHDL, untested:

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Now I'll connect the outputs and try to test this ...

RE: VIDOR 4000: Servo Interface

shabaz — Fri, 30 Jul 2021 15:11:28 GMT

Hi Jon,

Great blog, and very useful seeing how you implemented the SPI interface.. I've never tried that before, and want to give that a go sometime.

I've not used hobby servos often enough to know for sure, but I think 8-bit might not be enough, 9-bit could be better to see visible movement with some servos with a single bit change,

and ballpark 0.6msec to 2.4 msec pulse width allows for the servos that don't strictly obey the recommended range.

Still, these are just slight changes to the HDL if you experience that whenever you try the servos.

RE: VIDOR 4000: Servo Interface

Jan Cumps — Fri, 30 Jul 2021 10:16:16 GMT

I've tackled servos in VHDL earlier, but then I adapted a module from the internet.

I didn't start from scratch. I just removed the IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED libraries, as Michael suggests here.

But not for that reason. I read it they were to be avoided, but I didn't have the context provided by MK.

RE: VIDOR 4000: Servo Interface

michaelkellett — Fri, 30 Jul 2021 08:55:40 GMT

Thanks for the blog.

I'll offer a couple of suggestions re. the VHDL which I hope may be useful to you and others.

LIBRARIES

In your VHDL you have:

library IEEE;

use IEEE.std_logic_1164.all;

---use IEEE.numeric_std.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

The true standard is numeric_std and this should always be used.

ieee.std_logic_arith and ieee.std_logic_unsigned are not actually standards and have problems.

To get lots of information and opinion about why, I suggest Googling - ieee.std_logic_arith.

To my mind one of the major problems with ...arith and ... unsigned is that they break VHDLs strong typing.

For example, in your code you declare signal prescaler: std_logic_vector(7 downto 0);

and then later you have:

prescaler <= prescaler - 1;

Prescalar has been declared as std_logic_vector - which is group of logical bits. You use exactly the same declaration for servo_out.

The intention is that prescaler is an integer and that servo_out is 8 independent logic signal bits.

If you use numeric.std then you just can't subtract 1 from a std_logic_vector.

You would need to decalre it as signal prescaler unsigned(7 downto 0);

This is good because you are not able to make mistakes like servo_out <= servo_out - 1;

ARRAYS

If you made servo_hold and servo_data into arrays you could save a great deal of typing (and sources of error).

But even better you could easily make you code much more flexible so that the exact same code could give you 1, 2 ....n servos.

It wouldn't use any less resources but it would be much easier to maintain.

MEMORY BLOCK

You are using registers for servo_data and servo_hold, but as you mention the FPGA has a great many clock cycles available for

each pulse width step. You could use a memory block in the FPGA for the servo registers and easily manage as many as 64 with no loss of performance.

This is probably not worth the effort for 8 servos (swaps 128 registers for 1 memory block) but at 64 would swap 1024 regsiters for 1 memory block.

I hope this is useful.

RE: VIDOR 4000: Servo Interface

genebren — Thu, 29 Jul 2021 21:48:36 GMT

Nice blog on VHDL and servo signaling.