Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQ/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-ram-design-for-altera-cyclone-on-vivado-and-pynqStore 1024 12 bit values in a VHDL RAM design, and automatically test it. This post uses the VHDL RAM design of Michael Kellett on a Zynq. You can store data and read it back. The design was done out of curiousity. To see how and when Block RA...en-USTelligent Community 12RE: Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQhttps://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-ram-design-for-altera-cyclone-on-vivado-and-pynqWed, 01 Dec 2021 10:54:05 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:9d516a2a-aa6c-4ba4-8970-433c04654847Jan Cumps1<p>I&#39;m going to try and adapt this example for DMA use, to exchange data between the RAM and the Zynq&#39;s DRAM.</p> <p>It could be a portability gateway. Vendor specific logic to get the RAM written and read from Compute side. Generic VHDL from RAM to other FPGA IP.</p><img src="https://community.element14.com/aggbug?PostID=11623&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">RE: Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQhttps://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-use-ram-design-for-altera-cyclone-on-vivado-and-pynqTue, 03 Aug 2021 08:55:30 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:9d516a2a-aa6c-4ba4-8970-433c04654847michaelkellett0<p>Thanks Jan.</p><p>When I get my Xilinx tools running and the board I&#39;ll attempt similar project on an Artix 35 chip.</p><p>&nbsp;</p><p>MK</p><img src="https://community.element14.com/aggbug?PostID=11623&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">