Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

Jan Cumps — Sun, 29 Aug 2021 21:15:53 GMT

While I'm building up Shabaz' SDR, I'm refining the FPGA quadrature oscillator.

I'd like to make its frequency change in steps. Programmable from the Zynq ARM/Linux PS.

To prevent that I have to alter the quadrature oscillator VHDL, I'm adding a clock changer at the input of its clock input.

At this moment a naive one. A clock divider.

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The output frequency of the quadrature oscillator is always its input frequency / 8.

So if I divide the input clock by 2, the effective frequency is input / 16.

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

Andrew J — Thu, 05 Aug 2021 21:30:27 GMT

I‘m hoping to understand at least some of this by the end of summer! It’s impressive to develop so quickly

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

jc2048 — Thu, 05 Aug 2021 15:14:05 GMT

Here is another alternative, running on my VIDOR 4000.

[View:/resized-image/__size/480x234/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-828b79e0-2304-4e6d-b22b-47f04565d501/contentimage_5F00_208481.png:480:234]

But this one is bland and boring, because it's just a very simple finite-state machine. Here's the VHDL:

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RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

genebren — Wed, 04 Aug 2021 22:21:00 GMT

Jan,

Great work!

Just thinking out loud, but can't two of the clock signals be defined as 'not' of the other two clocks?

Gene

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

jc2048 — Wed, 04 Aug 2021 22:14:33 GMT

Or do you have an alternative?

Does the Zync clock block allow you to dynamically set the frequency under the control of either the processor or the fabric? If so, it may also give you the ability to produce four outputs at different phases. Then you don't need the logic at all.

The Cyclone 10 part seems to allow control of a PLL, though whether the resolution would be fine enough for sensible tuning of Shabaz's radio I don't know. I'm not sure how accurate the phase settings would be either, though it does seem to allow for adjusting phase.

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

shabaz — Wed, 04 Aug 2021 21:39:23 GMT

Hi Jan,

Great work, and impressively fast development.

The waveforms look excellent on the 'scope screenshot. Very good idea to do this on the FPGA!!

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

Jan Cumps — Wed, 04 Aug 2021 21:09:49 GMT

There is a subtle difference. The output is different during the first 3 clock ticks, until the very first full shift is completed.

That can be fixed by setting initial and reset values for buffer and counter to the state expected during a 4th tick.

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

fmilburn — Wed, 04 Aug 2021 20:54:00 GMT

Impressive that you did this so quickly and with so little code

RE: Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

Jan Cumps — Wed, 04 Aug 2021 20:37:08 GMT

The Vivado / Zynq / Pynq artifacts:

Block diagram:

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Constraints:

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Jupyter notebook:

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I've used one of the Zync fabric clocks as input. Any clock works, and output will be clock/4.

Here, the input clock was set to 4 MHz:

[View:/resized-image/__size/620x422/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-828b79e0-2304-4e6d-b22b-47f04565d501/3542.contentimage_5F00_208468.png:620:422]