<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Learning Xilinx Zynq: Hardware Accelerated Software</title><link>/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-hardware-accelerated-software</link><description>The main target for Zynq family FPGAs is: compute systems with hardware acceleration.
It&amp;#39;s architecture focuses on being able to stream data efficiently between ARM and FPGA submodules.
The FPGA can then perform manipulations in hardware that tak...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Learning Xilinx Zynq: Hardware Accelerated Software</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-hardware-accelerated-software</link><pubDate>Sun, 15 Aug 2021 14:28:53 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:0eb39390-7141-4d7e-b6a2-7ae1367120f4</guid><dc:creator>Jan Cumps</dc:creator><slash:comments>2</slash:comments><description>&lt;p&gt;I&amp;#39;m going to try make an own project with acceleration, now that I understand a bit how the development cycle ticks .&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=11643&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>