Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-try-to-make-my-own-accelerated-opencv-function---2-vivado-block-designRead this for info only. The project done at the time didn&#39;t work. I&#39;m leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.It works, and can easily be repeated, with Vitis HLSen-USTelligent Community 12RE: Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Designhttps://community.element14.com/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-try-to-make-my-own-accelerated-opencv-function---2-vivado-block-designMon, 16 Aug 2021 19:05:00 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d93b1570-537d-436a-a59e-cdc338b8970bJan Cumps1<p>Current status:</p><ul><li>both Vitis HLS and Vivado projects build successful.</li><li>in Jupyter, loading the bitstream and preparing the objects works. During execurtion of the accelerator, I get DMA errors:</li></ul><p><span>[View:/resized-image/__size/620x421/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-d93b1570-537d-436a-a59e-cdc338b8970b/8308.contentimage_5F00_208551.png:620:421]</span></p><img src="https://community.element14.com/aggbug?PostID=11663&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">