Summer of FPGAs - Building an Embedded System on FPGA

RE: Summer of FPGAs - Building an Embedded System on FPGA

navadeepganeshu — Sun, 29 Aug 2021 12:29:10 GMT

Again on Arty-S7, the rotary thing works fine the same way.

I tried to add another parameter "Status" which would detect if the user presses the rotary encoder's central switch so as to set the value back to 0 at any point. So, added a new AXI_GPIO 1 bit wide to read SW pin of rotary encoder and took that parameter into the same while loop with if(status == 0). It was just a lame idea of trying to make it, I realized after running the program.

The status does flip to 0 and so does the count. But when the switch is released, Status turns back to 1 as expected and counter resumes from the same point where it was before pressing that switch. Rather it was expected to start back from 0. So for this, would tweaking the quad_decode.v and adding in a new parameter to reset the full counter help? Any clues?

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RE: Summer of FPGAs - Building an Embedded System on FPGA

navadeepganeshu — Mon, 23 Aug 2021 17:08:18 GMT

Gave a try with ARTY S7 - 50. For this board, I skipped adding NOT logic for reset(lab video1) as it was active low with the onboard switch by default. Used GPIO0 and 1 for 4 x LEDs and 4 x pushbuttons. The hello word is here: (I didn't believe it worked and suspected "hello world" was out-of-the-box demo serial prints. But ya, with "It works!" It works.
All other steps are almost the same and were compatible with Vitis IDE(on 2020.1). Nice series,...following through.

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RE: Summer of FPGAs - Building an Embedded System on FPGA

Jan Cumps — Wed, 18 Aug 2021 21:06:47 GMT

Video 3 also worked perfectly on a Pynq-Z2 board with Zynq IC.

[View:https://www.youtube.com/watch?v=nMtRAoAfuwM:740:466]

RE: Summer of FPGAs - Building an Embedded System on FPGA

Jan Cumps — Tue, 17 Aug 2021 19:14:37 GMT

I'm at video 2, just finished the Vivado Block Diagram

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I did 2 things different:

my board doesn't have a UART that can be connected to the PL, so I made the transmit pin external and will use a 3V3 serial to USB converter to get the data.
I used a util_vector_logic block to create a NOT gate instead of coding. The effect is the same.

Validation works.

I'm having errors synthesizing: [Common 17-217] Failed to load feature 'core'.

That's because it's mandatory on the Zynq to place the PS ARM block.

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So I changed the design a little specific for the Zynq on my board:

added the Zync, and used it for the clock and the reset (so that it does not have to do nothing [View:/resized-image/__size/16x16/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-c117c06e-3a99-4702-9787-93585a4ff7c3/8562.contentimage_5F00_1.png:16:16])
removed the clock wizard, because it's not needed, see step above.
still kept your reset, but used it as an additional one, for the PL blocks only.

There is nothing wrong with your design, it's all because of the two ARM cores in my FPGA.

In Vivado 2020.2, the menu to start Vitis (instead of SDK) has moved:

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The startup is somewhat different. The hardware platform is not automatically loaded, but you can select the XSA exported from Vivado when creating an application project.

Because of the Zynq FPGA I'm using, the ARM processors are also available for doing development on, next to the MicroBlaze

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Then the result is more similar to the SDK look and feel:

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RE: Summer of FPGAs - Building an Embedded System on FPGA

Jan Cumps — Mon, 16 Aug 2021 19:38:50 GMT

[mention:851ab0f9941c487cabc3fe5a4f56d75e:e9ed411860ed4f2ba0265705b8793d05] , I'm working on a similar exercise. It's a race to keep up with tool version differences.

Since the 2019 chain that you're using, the SDK seems to be replaced by Vitis (not Vitis HLS).

The Xilinx solutions and workflows for these "Processor + FPGA" packages does not seem to have settled yet.

This makes it tricky to work with the application suite by following blogs and videos, if versions don't exactly match what you have installed.