<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Learning Xilinx Zynq: Logic Gates in Vivado</title><link>/technologies/fpga-group/b/blog/posts/learning-xilinx-zynq-logic-gates-in-vivado</link><description>When you&amp;#39;re working on a Vivado Block design, you can add IP.
There are 100s of options available. But you will not find a NOT gate, AND gate, ...
They are there though, available under the cryptical name Utility Vector Logic and Utility Reduced Logi</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>