/technologies/fpga-group/b/blog/posts/summer-of-fpga-workshop-4-elaborating-on-the-workshop-designIntroduction Workshop 4 of the Summer of FPGA series for the Ultra96-V2 board went through a design for using the Mezzanine Click board. It was covered &#39;at pace&#39; and this blog is my jottings on the steps taken, specifically elaborating on some o...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/summer-of-fpga-workshop-4-elaborating-on-the-workshop-designFri, 27 Aug 2021 22:33:25 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:fca8d4c2-68f9-4d22-bb07-fc249938e788bhfletcher1<p>Excellent explanations, <span>[mention:169a4014e923440aab0fa7af5203dabd:e9ed411860ed4f2ba0265705b8793d05]</span>. Thanks for sharing these additional details. </p><p>&nbsp;</p><p>Regarding the Tcl command syntax to disable <span>M_AXI_HPM1_FPD, I did the operation manually first, at which point I then copied the reported Tcl that showed up in the Tcl console. The sleuthing you&#39;ve done to relate this back to GP1 is beyond anything that I looked into.</span></p><p>&nbsp;</p><p><span>I do have a question regarding the Makefile in the Driver of the custom IP. Are you saying that you found the Makefile to be generated correctly when you completed all the steps in Vivado? If so, I&#39;m definitely interested in exploring what you did differently. Even after I copied the Makefile into the drivers directory at the beginning of the IP creation, I found it got overwritten later on. In the end, the way I created the XSA used in the Vitis part of Workshop #4 was by opening the XSA in 7-zip, deleting the bad Makefile, copying the good Makefile into the archive, and then re-saving the archive.</span></p><p>&nbsp;</p><p><span>Bryan</span></p><img src="https://community.element14.com/aggbug?PostID=11687&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">