/technologies/fpga-group/b/blog/posts/summer-of-fpga-workshop-4-elaborating-on-creating-custom-ipIntroduction Workshop 4 of the Summer of FPGA series for the Ultra96-V2 board went through a design for using the Mezzanine Click board. It was covered &#39;at pace&#39; and this blog is my jottings on the steps taken, specifically elaborating o...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/summer-of-fpga-workshop-4-elaborating-on-creating-custom-ipFri, 27 Aug 2021 22:55:42 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:b0343611-b63a-42d5-9433-a0a143a33d37bhfletcher1<p>Again, <span>[mention:169a4014e923440aab0fa7af5203dabd:e9ed411860ed4f2ba0265705b8793d05]</span> -- thanks for sharing! I think your extra steps and explanations will be very helpful to many others who come back to these recordings.</p><p>&nbsp;</p><p>One thing to note on the Makefile, I was also using Vivado 2021.1, but I was using Windows. I wonder if there is a difference here in Vivado operation in Windows vs. Linux. Xilinx has released a 2021.1.1 update, which I installed yesterday. I&#39;ll try running back through to see if anything changes.</p><p>&nbsp;</p><p>One other thing that I previously hadn&#39;t noticed was the &quot;Enable Interrupt Support&quot; during the Add Interfaces dialog. I&#39;d like to explore that a bit more to see what happens when you check that box since this IP does, in fact, have an interrupt.</p><p><span>[View:/resized-image/__size/224x312/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-b0343611-b63a-42d5-9433-a0a143a33d37/contentimage_5F00_208666.png:224:312]</span></p><p>&nbsp;</p><p>Well done!</p><p>Bryan</p><img src="https://community.element14.com/aggbug?PostID=11692&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">