<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>FPGA Design Guide Pt1</title><link>/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt1</link><description>Last month I looked at three different FPGA dev kits . You will have seen that I have selected the XuLA FPGA board from XESS that uses a Xilinx chip at its core. This month I want to go though the initial design process I use when designing a FPGA pro</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: FPGA Design Guide Pt1</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt1</link><pubDate>Tue, 31 Jan 2012 19:44:49 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:64d4650a-d0a3-4865-a326-a5dc48ed6d7c</guid><dc:creator>pjclarke</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Images have now been updated and removed from Google - hopfully you can all see them now without issues.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Thanks&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=13339&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: FPGA Design Guide Pt1</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt1</link><pubDate>Tue, 31 Jan 2012 05:45:59 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:64d4650a-d0a3-4865-a326-a5dc48ed6d7c</guid><dc:creator>davidbear</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;How much current can your FPGA sink?&amp;nbsp; I see you are using pnp driver, will you need a npn to sink all that current?&amp;nbsp; I do like where you are going with this it should be a valuable learning aid.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=13339&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: FPGA Design Guide Pt1</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt1</link><pubDate>Mon, 30 Jan 2012 19:36:07 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:64d4650a-d0a3-4865-a326-a5dc48ed6d7c</guid><dc:creator>Former Member</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice work tying all the physical parts together. &lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=13339&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: FPGA Design Guide Pt1</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt1</link><pubDate>Mon, 30 Jan 2012 19:19:07 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:64d4650a-d0a3-4865-a326-a5dc48ed6d7c</guid><dc:creator>fustini</dc:creator><slash:comments>2</slash:comments><description>&lt;p&gt;Hi Paul, I think the drawings on google docs are not allowing public viewing.&amp;nbsp; BTW, enjoyed listening to your interview on ZombieTech yesterday.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Cheers,&lt;/p&gt;&lt;p&gt;Drew&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=13339&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>