FPGA Design Guide Pt3

FPGA Design Guide Pt3/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt3So over the last few months if you have been following my FPGA Design guide you will see that I have first blocked out the chucks of logic I needed, then last time I showed you the code used to get my first part of the temperature display working. Hoen-USTelligent Community 12RE: FPGA Design Guide Pt3https://community.element14.com/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt3Sat, 17 Mar 2012 12:19:15 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:5534a30f-2e24-4d57-ac97-cbdf057340f2michaelkellett1<p>Paul - I'm baffled - have you tested counter_30bit ?</p><p> </p><p>You define:</p><p><span style="font-weight:normal;">signal cnt_r : std_logic_vector(29 downto 0) := (others=>'0');</span></p><p> </p><p><span style="font-weight:normal;">then later you have:</span></p><p> </p><p><span style="font-weight:normal;">cnt_r <= cnt_r + 1;</span></p><p> </p><p><span style="font-weight:normal;">But the + operator is not defined for std_logic_vector so it won't compile.</span></p><p> </p><p><span style="font-weight:normal;">Michael Kellett<br /></span></p><p><span style="font-weight:normal;"><br /></span></p><img src="https://community.element14.com/aggbug?PostID=13710&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">