/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt4---spi-interfaceSo now that I have a working display I guess I had better get started on the SPI temperature sensor. The design process here is a little different as we are not just passing data or signals from one block to the next. What we need is a sub block thaten-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt4---spi-interfaceSun, 11 Mar 2018 03:54:26 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:28d1c971-bfaf-40de-bada-7c37bdf1cc64cybero0<p>Hi Paul,</p><p>I&#39;m running your code I found something that looks like wrong.</p><p>You&#39;re sampling during 34 clock cycles instead 32.</p><p>&nbsp;</p><p>See the attached picture: <span>[View:/resized-image/__size/620x115/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-28d1c971-bfaf-40de-bada-7c37bdf1cc64/5355.contentimage_5F00_174779.png:620:115]</span></p><img src="https://community.element14.com/aggbug?PostID=13743&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/fpga-design-guide-pt4---spi-interfaceTue, 27 Feb 2018 12:25:54 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:28d1c971-bfaf-40de-bada-7c37bdf1cc64cybero1<p>Hi Paul, </p><p>Great job! I loved to find this entry in Google. Thanks for sharing your work.</p><p>There&#39;s something confusing in your design.</p><p>MAX31855 needs a 5MHz clock source. Your FPGA uses a 12MHz oscillator and I can&#39;t see a frequency divider in your design. SPI_clock comes from a 30 bit counter. Supposing clk_i comes from the 12MHz oscillator, that means SPI_clock is a 400KHz signal. Am I right?</p><p>&nbsp;</p><p>Can you please clarify how you get the 5MHz from your 12MHz oscillator?</p><p>&nbsp;</p><p>Thanks again.</p><p>Cheers.</p><img src="https://community.element14.com/aggbug?PostID=13743&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">