XXICC (21st Century Co-design) release 0.0p

RE: XXICC (21st Century Co-design) release 0.0p

johnbeetem — Fri, 29 May 2015 18:12:22 GMT

I just uploaded FlaviaLP56 rev 0.0p data files for the LOGI-Pi rev R1.2. You can now use pinout tables to map top-level ports and signal names to FPGA pins, and specify pull-up, pull-down, and keeper circuits for FPGA I/Os.

I've only tested FlaviaLP56 using JTAG, and only for LOGI-Pi rev R1.2. It probably won't work for LOGI-Pi-2 (R1.5.1). See the description at FlaviaLP56 rev 0.0p data files for details.

RE: XXICC (21st Century Co-design) release 0.0p

johnbeetem — Fri, 29 May 2015 16:56:52 GMT

I just uploaded FlaviaLB56 rev 0.0p data files for the LOGI-Bone R1.0. You can now use pinout tables to map top-level ports and signal names to FPGA pins, and specify pull-up, pull-down, and keeper circuits for FPGA I/Os.

I've only tested FlaviaLB56 using JTAG, and only for LOGI-Bone R1.0. It probably won't work "out of the box" for LOGI-Bone-2 (R1.5.1). See the description at FlaviaLB56 rev 0.0p data files for details.