/technologies/fpga-group/b/blog/posts/gradient-filter-implementation-on-fpga-part-3-debugging-in-hdlThis blog is part 3 of a 4 part series of implementing a gradient filter on an FPGA. If you have not already read the earlier parts see the link below to get up to speed before reading this blog. Additionally the user can catch some of ou...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/gradient-filter-implementation-on-fpga-part-3-debugging-in-hdlTue, 14 Jul 2015 12:08:05 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:710decdf-105e-423c-adb4-ac5b8e6da5dfpeepo0<p>This is a really excellent tutorial as I worked my way through,</p><p>&nbsp;</p><p>but had trouble right at the end: <a class="jive-link-external-small" href="http://peepo.com/media/xilinx_test_bed.png" rel="nofollow ugc noopener" target="_blank" title="http://peepo.com/media/xilinx_test_bed.png">http://peepo.com/media/xilinx_test_bed.png</a></p><p>&nbsp;</p><p>the simulator finished, but I cannot immediately, clearly and simply reconcile the result with the inputs.</p><p>&nbsp;</p><p>perhaps I missed something?</p><p>&nbsp;</p><p>or perhaps you could add a description?</p><p>&nbsp;</p><p>or maybe I will understand further in the morning?</p><p>&nbsp;</p><p>~:&quot;</p><img src="https://community.element14.com/aggbug?PostID=21116&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">