/technologies/fpga-group/b/blog/posts/cpld-egg-timerIntroduction Quick little project to make an egg timer using the MAX II board that I bought over the summer. Initially, I&#39;ll just have it counting down from three minutes. If I feel suitably inspired later, I might extend it to allow setting t...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/cpld-egg-timerTue, 02 Nov 2021 08:13:35 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d279cc4d-5ae8-43d7-9081-3a1463e062b1Jan Cumps1<p>Here&#39;s how Xess library hanles led segment displays: <a class="jive-link-external-small" href="https://github.com/xesscorp/VHDL_Lib/blob/master/LedDigits.vhd" rel="nofollow ugc noopener" target="_blank" title="https://github.com/xesscorp/VHDL_Lib/blob/master/LedDigits.vhd">https://github.com/xesscorp/VHDL_Lib/blob/master/LedDigits.vhd</a> </p><img src="https://community.element14.com/aggbug?PostID=22106&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/cpld-egg-timerMon, 01 Nov 2021 19:40:47 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d279cc4d-5ae8-43d7-9081-3a1463e062b1genebren2<p>Really cool little project.&nbsp; You need some sort of &quot;Beep, Beep, Beep&quot; to signal that the egg is ready.</p><img src="https://community.element14.com/aggbug?PostID=22106&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/cpld-egg-timerMon, 01 Nov 2021 17:52:30 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:d279cc4d-5ae8-43d7-9081-3a1463e062b1rsjawale241<p>Great! Been a long time since I saw a CPLD based project. </p><img src="https://community.element14.com/aggbug?PostID=22106&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">