PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-trainingPYNQ now supports Vivado and Vitis HLS version 2020.2 (since PYNQ 2.7).Time to re-check the hardware accelerator mechanisms, with DMA. This workflow has now stabilised. Hardware Acceleration is the technique to implement program logic insi...en-USTelligent Community 12RE: PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IPhttps://community.element14.com/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-trainingMon, 03 Jan 2022 22:44:21 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:fc83a27c-11b8-4763-8e85-8cdea2ab61b9Jan Cumps1<p>Warning if you&#39;re using Vitis HLS. The platform is impacted by a Year2022 bug:&nbsp;<a href="https://support.xilinx.com/s/question/0D52E00006uxnnFSAQ/2022-timestamp-overflow-error-2201011128-is-an-invalid-argument-please-specify-an-integer-value?language=en_US">https://support.xilinx.com/s/question/0D52E00006uxnnFSAQ/2022-timestamp-overflow-error-2201011128-is-an-invalid-argument-please-specify-an-integer-value?language=en_US</a></p> <p>TL;DR: you need to set the clock to a 2021 date to build a design. All recent Vitis HLS versions are affected.</p><img src="https://community.element14.com/aggbug?PostID=22365&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">RE: PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IPhttps://community.element14.com/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-trainingFri, 26 Nov 2021 12:04:47 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:fc83a27c-11b8-4763-8e85-8cdea2ab61b9Jan Cumps0<p>The generated IP block contains the VHDL and Verilog source.<br />This source should not be edited&nbsp;and isn&#39;t intended for human consumption. Her&#39;s a snippet anyway:<br /><br /></p> <p>[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:f2a58c81-0d0c-40be-96c7-7fe2435b2705:type=text&text=constant%20ap_const_lv32_5%20%3A%20STD_LOGIC_VECTOR%20%2831%20downto%200%29%20%3A%3D%20%2200000000000000000000000000000101%22%3B%0D%0A--%0D%0AB_TDATA_int_regslice%20%3C%3D%20std_logic_vector%28unsigned%28A_TDATA_int_regslice%29%20%2B%20unsigned%28ap_const_lv32_5%29%29%3B]</p><img src="https://community.element14.com/aggbug?PostID=22365&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">