PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design

PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-training---part-2-add-the-accelerated-ip-to-a-vivado-designI'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience. Register the IP and Use it in Vivado In part 1, we made the hardware a...en-USTelligent Community 12RE: PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado designhttps://community.element14.com/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-training---part-2-add-the-accelerated-ip-to-a-vivado-designSat, 27 Nov 2021 13:56:33 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:505a2795-5be8-4ba8-9050-0190265f3fb8Jan Cumps0<p>I've created a separate post to look at the different data flows: <a href="/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-training---deep-dive-the-data-streams-between-accelerator-ip-and-arm-processors">Deep Dive: the data streams between Accelerator IP and ARM processors</a>.<br />That article shows how the data flows between DRAM and the Accelerator IP.</p><img src="https://community.element14.com/aggbug?PostID=22367&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">