/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-training---part-3-use-the-hardware-accelerated-code-in-softwareI&#39;m following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience. Use the Accelerated function in Software In part 1, we made the hardwa...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-training---part-3-use-the-hardware-accelerated-code-in-softwareSun, 28 Nov 2021 20:12:23 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:84425e56-fbf2-4d8f-8c4d-6655793248c0Jan Cumps2<p>What this example doesn&#39;t how, is that you don&#39;t have to use this as an accelerator for software. <br />You can also use it directly in an FPGA flow.</p> <p>As an example, you could flow the data from&nbsp;the on-board ADC into your FPGA datastream, or to a MicroBlaze with DMA.<br /><br /></p> <p>Check this blog: <a href="https://www.hackster.io/adam-taylor/signal-processing-with-xadc-and-pynq-3c716c">https://www.hackster.io/adam-taylor/signal-processing-with-xadc-and-pynq-3c716c</a>.&nbsp;<br />I&#39;m going to try this one of these days.</p><img src="https://community.element14.com/aggbug?PostID=22371&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">