/technologies/fpga-group/b/blog/posts/pynq-and-zynq-the-vitis-hls-accelerator-with-dma-training---deep-dive-the-data-streams-between-accelerator-ip-and-arm-processorsThis is a supporting post for Part 2: Add the Accelerated IP to a Vivado design .I'm untangling the different data streams.There are 3 types of data exchanged between the FPGA and ARM parts of the Zynq: "Business Data": the inputs and outputs to...en-USTelligent Community 12