RE: Reasons to switch from Spartan-6 to Spartan-7 FPGAs #1

michaelkellett — Tue, 31 May 2022 08:41:34 GMT

In your description of the Spartan 7 DSP block you say:

Architecturally, the DSP48E1 provided in 7 series devices also enables the implementation of an Algorithmic Logic Unit (ALU) and enables support of Single Instruction Multiple Data (SIMD) mode which allows increased throughput.

According to the Xlinix/AMD documentation (UG749):

• Unique features in DSP48E1 over DSP48A1:
• Arithmetic logic unit (ALU)
• SIMD mode

The term ALU has been conventionally used to describe an Arithemetic and Logic Unit which is the resource actually present in the series 7 FPGA.

This mistake is also present in the Avnet document (attributed to Adiuvo by Adam Taylor) to which you link at:

https://www.avnet.com/wps/wcm/connect/onesite/151ef5b4-03a6-4063-aadb-3c0567f39d34/migrating-s6-to-7series.pdf?MOD=AJPERES&CVID=nXBmgN3&CVID=nXBmgN3&attachment=false&id=1645663957158

So I suggest a challenge for you:

To demonstrate using a DSP block as an ALU using VHDL (instantiation or inference as you choose) - this would be something that you can't do on a Spartan 6.

The project should be as simple as possible (ie no microblazes, complex busses or other distractions).

Input and output by logic level UART to PMOD pins is best.

This project is ideally suited to Xilinx under the new ownership of AMD, as a tribute to one of AMD's best ever parts, the AM2900 series bit slice processor [emoticon:fbd079a1c4f748c5a234faee215de9cc]