Arty S7 50 First Baremetal Software Project

RE: Arty S7 50 First Baremetal Software Project

Jonathan101 — Wed, 11 Jan 2023 14:02:00 GMT

Hello and thanks for the tutorial. Does this tutorial apply also for Arty A7 35T board?

RE: Arty S7 50 First Baremetal Software Project

Jan Cumps — Fri, 15 Jul 2022 21:53:42 GMT

When the Memory Interface Generator is put on the board, it creates a sys_clk_i port.
To stay consistent with the rest of the design, where board assets (e.g. the DDR3 SDRAM) are used, you can remove the port, and drag the board asset DDR Clock on the design and connect that. It will then automatically deal with the constraints.

RE: Arty S7 50 First Baremetal Software Project

saadtiwana_int — Tue, 28 Jun 2022 09:08:10 GMT

Thanks a lot for your detailed post. Helped me solve an issue with my microblaze hello world project.

In your post you wrote "If your design requires more clocks than just the ui_clk provided by the MIG, you will need to add a clocking wizard IP that is driven by the MIG's ui_clk". May I know why it's necessary to use MIG's ui_clk as a source to generate any other clocks? For example, can i put a Clocking Wizard on the 100Mhz/12Mhz board clocks and use the generated frequencies to drive peripherals connected to the microblaze?

Or, if you can point me to a source where you got this information, so i may read further on this.

Thanks,

Saad

RE: Arty S7 50 First Baremetal Software Project

javagoza — Sun, 05 Jun 2022 18:18:30 GMT

I still don't have the pmodHygro module but it seems that the software and the FPGA configuration work correctly. I see data through the I2C port created in the JA PMOD interface

0x40, // Chip address of PmodHYGRO IIC

RE: Arty S7 50 First Baremetal Software Project

javagoza — Sun, 05 Jun 2022 17:37:18 GMT

Following Jayson Bethurem workshop Arty-S7 Workshop: Part 3: Rapid Sensor Prototyping with Digilent Peripheral Modules I've been able to add a PmodHYGRO IP.

The bitstream has been generated. I only had to add a constrains file to define a few ports of the pmod interface that remained to be defined.

...

RE: Arty S7 50 First Baremetal Software Project

javagoza — Sun, 05 Jun 2022 16:28:01 GMT

I have learned a lot doing this tutorial following Digilent's guide.
There are many ways to do the same thing.
For those who want to start quickly, my recommendation is to start with this workshop

Arty-S7 Workshop: Part 2: Building a Custom Microcontroller in Minutes

by Jayson Bethurem Product Line Manager: Spartan, Artix, Zynq-7000, Zynq UltraScale+ at Xilinx

Jayson does it the smart way!

RE: Arty S7 50 First Baremetal Software Project

michaelkellett — Sun, 05 Jun 2022 13:55:24 GMT

Thanks for writing all that down !

I identified about 70 critical non-intuitive steps in building the hardware, followed by about 17 steps to get the software running.

Not for the faint hearted !

RE: Arty S7 50 First Baremetal Software Project

Andrew J — Sun, 05 Jun 2022 08:25:50 GMT

There’s quite some work here, nice and detailed.