/technologies/fpga-group/b/blog/posts/try-the-digilent-xadc-demoDigilent has a set of demo projects for the Arty board. I&#39;m reviewing Arty XADC Demo . I&#39;m going to make a project with an analogue sensor, and that project is a good starting point. Migrate the Demo from 2016.4 The demo was written for Vivado 2016.4en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/try-the-digilent-xadc-demoFri, 24 Jun 2022 19:44:19 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8017ca73-35c8-40c5-97f4-ef31922cfbf5Jan Cumps0<p><strong>Related:&nbsp;Migrate the Digilent Arty S7-50 General I/O Demo&nbsp;(to latest board file)</strong></p> <p>Download the <a href="https://github.com/Digilent/Arty-S7-50-GPIO/releases" rel="noopener noreferrer" target="_blank">latest release full project archive</a>&nbsp;and extract it. Before opening it in Vivado,&nbsp;edit&nbsp;Arty-S7-50-GPIO.xpr</p> <pre># &lt;Option Name=&quot;BoardPart&quot; Val=&quot;digilentinc.com:arty-s7-50:part0:1.0&quot;/&gt;<br /> &lt;Option Name=&quot;BoardPart&quot; Val=&quot;digilentinc.com:arty-s7-50:part0:1.1&quot;/&gt;</pre> <p>Open the project, generate bitfile, program, enjoy</p> <p><img height="169" src="/resized-image/__size/648x338/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-8017ca73-35c8-40c5-97f4-ef31922cfbf5/pastedimage1656099832779v1.png" width="324" alt=" " /></p><img src="https://community.element14.com/aggbug?PostID=23855&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/try-the-digilent-xadc-demoFri, 24 Jun 2022 13:38:48 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8017ca73-35c8-40c5-97f4-ef31922cfbf5Jan Cumps0<p>XADC tip (works on a Zynq too):<br />Via the hardware manager, you can always check the device&#39;s XADC values. No matter what design is running (or not) running) on the FPGA.</p> <p><img src="/resized-image/__size/1280x720/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-8017ca73-35c8-40c5-97f4-ef31922cfbf5/pastedimage1656077870640v1.png" alt=" " /></p><img src="https://community.element14.com/aggbug?PostID=23855&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/try-the-digilent-xadc-demoFri, 24 Jun 2022 12:30:02 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:8017ca73-35c8-40c5-97f4-ef31922cfbf5Jan Cumps0<p>This project show how to use Vivado without block diagram or HDL wrapper. It&#39;s a single source Verilog design.</p><img src="https://community.element14.com/aggbug?PostID=23855&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">