<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Arty: talk to SPI EEPROM - part 1: hardware and modules</title><link>/technologies/fpga-group/b/blog/posts/arty-talk-to-spi-eeprom</link><description>Goal: write a design that exchanges data with an external EEPROM IC. I have a set of 25LC256 SPI 256 Kbit EEPROMs, so I&amp;#39;ll see if I can communicate with them, in VHDL.At this point, I&amp;#39;m not going to use the Xilinx MicroBlaze ...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Arty: talk to SPI EEPROM - part 1: hardware and modules</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/arty-talk-to-spi-eeprom</link><pubDate>Sat, 25 Jun 2022 20:01:49 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1e3c6383-545a-4666-bb39-673b451d01b1</guid><dc:creator>genebren</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice catch on the I2C versus SPI interfaces.&amp;nbsp; Good luck moving forward on this design.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=23860&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Arty: talk to SPI EEPROM - part 1: hardware and modules</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/arty-talk-to-spi-eeprom</link><pubDate>Sat, 25 Jun 2022 19:21:33 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1e3c6383-545a-4666-bb39-673b451d01b1</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;It is always good to check interfaces several times before you connect and test them.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=23860&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: Arty: talk to SPI EEPROM - part 1: hardware and modules</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/arty-talk-to-spi-eeprom</link><pubDate>Sat, 25 Jun 2022 19:19:21 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:1e3c6383-545a-4666-bb39-673b451d01b1</guid><dc:creator>Jan Cumps</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;The&amp;nbsp;SPI module I selected won&amp;#39;t do.&amp;nbsp;It will hold CS low until the requested data size is sent. But that&amp;#39;s a fixed size. The EEPROM has requirements to hold the CS until a activity is completed. In my case, that can be 1 byte (an instruction, or 4 bytes: instruction, 2 byte address, data).&lt;/p&gt;
&lt;p&gt;I can either adapt the current one I&amp;#39;m using - add an input parameter telling for how many bytes to hold the CS low, or look for an other one...&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=23860&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>