/technologies/fpga-group/b/blog/posts/vivado-how-to-override-generic-valuesIn HDL languages, you can define generics. These are values that are assumed by default, but can be overridden. In VHDL, this may look like this: ENTITY spi_master IS GENERIC( data_length : INTEGER := 16); --data length in bits PORT( ...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/vivado-how-to-override-generic-valuesMon, 27 Jun 2022 16:21:55 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:a919ca87-f79b-44ff-98d3-e204f3fef344dang740<p>Thanks for this pointer.&nbsp; It should come in handy once I start exploring Vivado a bit more.</p><img src="https://community.element14.com/aggbug?PostID=23862&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/vivado-how-to-override-generic-valuesSun, 26 Jun 2022 01:15:50 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:a919ca87-f79b-44ff-98d3-e204f3fef344wolfgangfriedrich1<p>I just had a nightmare vision of the Vivado Block design being a distant relative of Labview.</p><img src="https://community.element14.com/aggbug?PostID=23862&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">