online lesson: clock domain crossing with a VHDL frequency counter - part 1: simulation in Vivado

online lesson: clock domain crossing with a VHDL frequency counter - part 1: simulation in Vivado/technologies/fpga-group/b/blog/posts/online-lesson-clock-domain-crossingWhen your design has more than a single clock, you'll have to deal with cross-clock-domain situations. In my search for good online trainings, I bumped on this example from SURF-VHDL: How to compute the frequency of a clock . In this example, you haveen-USTelligent Community 12RE: online lesson: clock domain crossing with a VHDL frequency counter - part 1: simulation in Vivadohttps://community.element14.com/technologies/fpga-group/b/blog/posts/online-lesson-clock-domain-crossingWed, 06 Jul 2022 10:19:32 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:2939f47c-c715-47ac-86d7-de4025a19929michaelkellett2<p>Hello Jan,</p> <p>Since you are using Xilinx parts you might like to consider Xilinx's suggestions to:</p> <p>1) use synchronous resets by default</p> <p>2) not reset stuff unless you actually need to</p> <p><a href="https://docs.xilinx.com/r/en-US/ug1387-acap-hardware-ip-platform-dev-methodology/Synchronous-Reset-vs.-Asynchronous-Reset">https://docs.xilinx.com/r/en-US/ug1387-acap-hardware-ip-platform-dev-methodology/Synchronous-Reset-vs.-Asynchronous-Reset</a></p> <p></p> <p>MK</p><img src="https://community.element14.com/aggbug?PostID=23913&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">