<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Blog 1: Getting Started with FPGAs using VHDL</title><link>/technologies/fpga-group/b/blog/posts/blog-1-getting-started-with-fpgas-using-vhdl</link><description>Hello everyone, I&amp;#39;m among the selected challengers for the 7 ways to leave your Spartan-6 design challenge. Firstly I would like to thank the e14 community for providing me with the Arty S7 FPGA board. This will be my first FPGA board, having one of </description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: Blog 1: Getting Started with FPGAs using VHDL</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/blog-1-getting-started-with-fpgas-using-vhdl</link><pubDate>Tue, 13 Aug 2024 10:10:23 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:f630fcf9-699e-4ed8-bb10-ab0d7d168afc</guid><dc:creator>WDV</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;HI, I a student and I need your help for my project, I using zynq7000, and I have to initial ssd1322 via spi. But I already using spi from&amp;nbsp;&lt;a id="" href="https://forum.digikey.com/t/spi-3-wire-master-vhdl/12743" rel="noopener noreferrer nofollow" target="_blank" data-e14adj="t"&gt;https://forum.digikey.com/t/spi-3-wire-master-vhdl/12743&lt;/a&gt;. And try to create the rtl to support with OLED SSD1322. But I still stuck.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=23995&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>