/technologies/fpga-group/b/blog/posts/interacting-with-ddr3-sdram-on-arty-s7-50-7-ways-to-leave-your-spartan-6-fpgaIntroduction: The Arty S7 contains a 256MB DDR3L SDRAM with a 16-bit bus. For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The easiest way to accomplish this on t...en-USTelligent Community 12