<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>RC6 cipher implemented in Verilog</title><link>/technologies/fpga-group/b/blog/posts/rc6-cipher-implemented-in-verilog</link><description>Hello everyone. I welcome you to this blog post describing my project as part of 7 Ways to Leave Your Spartan-6 FPGA contest.
In this blog post I will describe my core project as part of this competition. As part of this competition I originally prom</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator></channel></rss>