<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>SystemVerilog Study Notes. BCD Number Format. RTL Combinational Circuit</title><link>/technologies/fpga-group/b/blog/posts/systemverilog-study-notes-bcd-number-format-rtl-combinational-circuit</link><description>Finishing up with combinational circuit design exercises in System Verilog. This time we are going to do exercises on another representation of numbers, BCD (binary-coded decimal format)

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 Binary-coded decimal 
 1-digit BCD incremen</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: SystemVerilog Study Notes. BCD Number Format. RTL Combinational Circuit</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/systemverilog-study-notes-bcd-number-format-rtl-combinational-circuit</link><pubDate>Tue, 11 Oct 2022 19:23:13 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:f3e5e740-8bc8-4f3a-967e-e9b084b0e004</guid><dc:creator>DAB</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;Nice post.&lt;/p&gt;
&lt;p&gt;It has been decades since I thought about BCD.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=24330&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>