/technologies/fpga-group/b/blog/posts/xula2-fpga---first-impressions-of-the-development-toolsI purchased a Xess XuLA2 . It arrived this morning.This post is the story of my first steps I have a little bit of experience with FPGAs. I learned digital electronics in the early-to-mid 80&#39;s. My VHDL skills are beginner level and I&amp;#3...en-USTelligent Community 12https://community.element14.com/technologies/fpga-group/b/blog/posts/xula2-fpga---first-impressions-of-the-development-toolsThu, 06 Apr 2017 00:43:01 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7d3566d5-a4b6-4997-a44d-bbfc9b49380avolly0<p><span>[mention:acaf6a9338de4eef8f6717d5561ed01d:e9ed411860ed4f2ba0265705b8793d05]</span></p><p>&nbsp;</p><p>Great Stuff!!</p><img src="https://community.element14.com/aggbug?PostID=2464&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">https://community.element14.com/technologies/fpga-group/b/blog/posts/xula2-fpga---first-impressions-of-the-development-toolsSat, 28 Jan 2017 21:56:02 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:7d3566d5-a4b6-4997-a44d-bbfc9b49380aJan Cumps0<p>A quick update on loading the bitstream to the on-board flash:</p><p>&nbsp;</p><p>When you use the technique above to send a bitstream to the fpga, it&#39;s volatile. Once the device is powered off, the configuration is gone.</p><p>To have your design active whenever the board is powered, store the bitstream to the on-board flash</p><p>Use these settings (see also the <a class="jive-link-external-small" href="http://www.xess.com/static/media/manuals/XuLA2-manual.pdf" rel="nofollow ugc noopener" target="_blank">manual for the XuLA2</a>):</p><p>&nbsp;</p><p>In ISE, set the following parameters, by right-clicking on the <em>Generate Program File</em> node</p><p><span>[View:/resized-image/__size/489x772/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-7d3566d5-a4b6-4997-a44d-bbfc9b49380a/contentimage_5F00_188140.png:489:772]</span></p><p>&nbsp;</p><ul><li>Configuration Options -&gt; ConfigRate : 10 MHz or higher (not important when programming the FPGA directly)</li><li>Startup Options -&gt; StartUpClk : CCLK (set it to JTAG if you beam directly to FPGA)</li></ul><p>&nbsp;</p><p>ReRun the bit stream generation, then issue the xsload command. Use the --flash option instead of --fpga</p><p>&nbsp;</p><p>[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=c_cpp&amp;text=xsload+--flash+blinker.bit]</p><div></div><p>&nbsp;</p><p>That&#39;s it.</p><img src="https://community.element14.com/aggbug?PostID=2464&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">