RE: XuLA2 FPGA - PWM with Dead Band in VHDL

Jan Cumps — Mon, 07 Jun 2021 12:25:35 GMT

The same code as above, on the Pynq-Z2. Rotary replaced by values coming out of the Zynq ARM cores.

The VHDL design and bitstream build is done in Vivado

[View:/resized-image/__size/620x268/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-30e3e134-12ba-48ce-8ffd-98ba70474ad7/8561.contentimage_5F00_208023.png:620:268]

4: the ARM cores

3: the PWM design of XESS, with the same modifications as in the blog above to get complimentary outputs and dead time generation.

the 125 MHz clock is directly sent to the PWM. Output frequency is dependent on the precision (bit length) of duty_i.

1: a slice to take 8 bits for duty_i out of the ARM 64 bit output bus

2: a slice to take 4 bits for band_i out of the ARM 64 bit output bus

The adapted VHDL (check here for original):

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=text&text=--**********************************************************************%0A--+Copyright+%28c%29+2011-2014+by+XESS+Corp+%3Chttp%3A%2F%2Fwww.xess.com%3E.%0A--+All+rights+reserved.%0A--%0A--+This+library+is+free+software%3B+you+can+redistribute+it+and%2For%0A--+modify+it+under+the+terms+of+the+GNU+Lesser+General+Public%0A--+License+as+published+by+the+Free+Software+Foundation%3B+either%0A--+version+3.0+of+the+License%2C+or+%28at+your+option%29+any+later+version.%0A--+%0A--+This+library+is+distributed+in+the+hope+that+it+will+be+useful%2C%0A--+but+WITHOUT+ANY+WARRANTY%3B+without+even+the+implied+warranty+of%0A--+MERCHANTABILITY+or+FITNESS+FOR+A+PARTICULAR+PURPOSE.++See+the+GNU%0A--+Lesser+General+Public+License+for+more+details.%0A--+%0A--+You+should+have+received+a+copy+of+the+GNU+Lesser+General+Public%0A--+License+along+with+this+library.++If+not%2C+see+%0A--+%3Chttp%3A%2F%2Fwww.gnu.org%2Flicenses%2F%3E.%0A--**********************************************************************%0A%0A--*********************************************************************%0A--+Modules+for+generating+repetitive+or+single+pulses.%0A--*********************************************************************%0Alibrary+IEEE%3B%0Ause+IEEE.std_logic_1164.all%3B%0A%0Apackage+PulsePckg+is%0A%0A++constant+HI+++%3A+std_logic+%3A%3D+%271%27%3B%0A++constant+LO+++%3A+std_logic+%3A%3D+%270%27%3B%0A++constant+ONE++%3A+std_logic+%3A%3D+%271%27%3B%0A%0A--*********************************************************************%0A--+PWM+module.%0A--*********************************************************************%0A++component+Pwm+is%0A++++port+%28%0A++++++clk_i++%3A+in++std_logic%3B+++++++++++--+Input+clock.%0A++++++duty_i+%3A+in++std_logic_vector%3B++++--+Duty-cycle+input.%0A++++++band_i+%3A+in++std_logic_vector%3B++++--+number+of+clock-ticks+to+keep+both+signals+low+before+rising+edge%0A++++++pwmA_o++%3A+out+std_logic%3B++++++++++--+PWM+output.%0A++++++pwmB_o++%3A+out+std_logic+++++++++++--+PWM+output+inverse.%0A++++++%29%3B%0A++end+component%3B%0A%0Aend+package%3B%0A%0A%0A--*********************************************************************%0A--+PWM+module.%0A--*********************************************************************%0A%0Alibrary+IEEE%2C+UNISIM%3B%0Ause+IEEE.MATH_REAL.all%3B%0Ause+IEEE.std_logic_1164.all%3B%0Ause+IEEE.numeric_std.all%3B%0Ause+UNISIM.vcomponents.all%3B%0Ause+WORK.PulsePckg.all%3B%0A%0Aentity+Pwm+is%0A++port+%28%0A++++clk_i++%3A+in++std_logic%3B+++++++++++++--+Input+clock.%0A++++duty_i+%3A+in++std_logic_vector+%287+downto+0%29%3B++++++--+Duty-cycle+input.%0A++++band_i+%3A+in++std_logic_vector+%283+downto+0%29%3B++++++--+number+of+clock-ticks+to+keep+both+signals+low+before+rising+edge%0A++++pwmA_o++%3A+out+std_logic%3B++++++++++++--+PWM+output.%0A++++pwmB_o++%3A+out+std_logic+++++++++++++--+PWM+output+inverse.%0A++++%29%3B%0Aend+entity%3B%0A%0Aarchitecture+arch+of+Pwm+is%0A++constant+MAX_DUTY_C+%3A+std_logic_vector%28duty_i%27range%29+%3A%3D+%28duty_i%27range+%3D%3E+ONE%29%3B%0A++signal+timer_r++++++%3A+natural+range+0+to+2**duty_i%27length-1%3B%0Abegin%0A%0A++process%28clk_i%29%0A++begin%0A++++if+rising_edge%28clk_i%29+then%0A%0A++++++pwmA_o+++%3C%3D+LO%3B%0A%0A++++++timer_r+%3C%3D+timer_r+%2B+1%3B%0A++++++if+timer_r+%3E%3D+unsigned%28band_i%29+%2B+unsigned%28duty_i%29+then%0ApwmB_o+%3C%3D+HI%3B%0Aend+if%3B%0A%0A++++++if+timer_r+%3C+unsigned%28duty_i%29+then%0A++++++++pwmB_o+%3C%3D+LO%3B%0A++++++++if+timer_r+%3E%3D+unsigned%28band_i%29++then%0ApwmA_o+%3C%3D+HI%3B%0A++end+if%3B%0A++++++end+if%3B%0A++++end+if%3B%0A++end+process%3B%0A++%0Aend+architecture%3B]

The Jupyter book, loading the bitstream and preparing the bits for duty_i and band_i:

[View:/resized-image/__size/620x232/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-30e3e134-12ba-48ce-8ffd-98ba70474ad7/7065.contentimage_5F00_208024.png:620:232]

Setting the values for 50% duty, 7 clock ticks dead time:

[View:/resized-image/__size/620x141/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-30e3e134-12ba-48ce-8ffd-98ba70474ad7/1207.contentimage_5F00_208025.png:620:141]

Result:

[View:/resized-image/__size/620x423/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-30e3e134-12ba-48ce-8ffd-98ba70474ad7/1602.contentimage_5F00_208026.png:620:423]

Customer action photo:

[View:/resized-image/__size/620x359/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-30e3e134-12ba-48ce-8ffd-98ba70474ad7/5415.contentimage_5F00_208027.png:620:359]

Detailed post: Learning Xilinx Zynq: port a Spartan 6 PWM example to Pynq

RE: XuLA2 FPGA - PWM with Dead Band in VHDL

clem57 — Sun, 05 Feb 2017 05:32:38 GMT

A little off subject: How many NAND gates can I implement on this FPGA (approximate if large). Currently I am taking course online and we are studying how to build a computer.

Clem

RE: XuLA2 FPGA - PWM with Dead Band in VHDL

clem57 — Sat, 04 Feb 2017 13:53:28 GMT

Just wondering can this be handled by an Arduino since the duty cycle time is 47 KHz and you use a PLC of 12 Mhz?

RE: XuLA2 FPGA - PWM with Dead Band in VHDL

Jan Cumps — Sat, 04 Feb 2017 12:42:02 GMT

Here are two captures to validate if the deadband matches the value I've set in the design (I've set it to 16 ticks):

[View:/resized-image/__size/805x484/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-30e3e134-12ba-48ce-8ffd-98ba70474ad7/contentimage_5F00_188142.png:805:484]

[View:/resized-image/__size/803x483/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-30e3e134-12ba-48ce-8ffd-98ba70474ad7/contentimage_5F00_188143.png:803:483]

If you count the purple ticks between the cursors for both transitions, they are 16 - a match.

To get this capture, I routed the input clock to a pin. That allows to probe it and count the ticks during the dead time.

I configured one of the FPGAs as the output pin, and named the signal chanclk_o.

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=text&text=%23+PM1+connections+for+clock+-+only+needed+for+probing%2C+no+functional+purpose.%0Anet+chanclk_o+++loc%3Dt7%3B]

In the port definition for my design, I added that we have this additional pin:

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=text&text=entity+Rotary_Pwm+is%0A++++Port+%28+clk_i+++++++%3A+in+++STD_LOGIC%3B%0A+++++++++++rotEncA_i+++%3A+in+++std_logic%3B++++++++--+Rotary+encoder+phase+1+output.%0A+++++++++++rotEncB_i+++%3A+in+++std_logic%3B++++++++--+Rotary+encoder+phase+2+output.%0A+++++++++++pwmA_o++++++%3A+out++STD_LOGIC%3B%0A+++++++++++pwmB_o++++++%3A+out++STD_LOGIC%3B%0A+++++++++++chanclk_o+++%3A+out++STD_LOGIC++%0A+++%29%3B%0Aend+Rotary_Pwm%3B]

And in the Behavioral section I linked the clock signal to that pin.

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=text&text=++++++%29%3B%0A%0A++chanclk_o+%3C%3D+clk_i%3B%0A%0Aend+Behavioral%3B]

That's all - at this point the clock is available on StickIt! motherpoard connector PM1, pin D1.