SystemVerilog Study Notes. FPGA ADSR envelope generator for sound synthesis (I)

RE: SystemVerilog Study Notes. FPGA ADSR envelope generator for sound synthesis (I)

michaelkellett — Mon, 13 Mar 2023 09:56:47 GMT

Good stuff, thanks for posting.

I think you are using linear against time increases and decreses of the amplitude.

You would get different (and more natural sounding) effects if you used logarithmic amplitude steps.

There are two ways (at least) that you could approach this.

The simplest way to do this is: :

envelope *= adsr step

The adsr step is best imagined as 1 +/- k, where k is usually <<1

If you want a long time constant you will end up with a very small value for k (with 96kHz sampling and 20dB amplitude change in 1 second, k = 0.000024). This can be handled very efficiently by fixed point multiplication and addition but takes some careful bit shifting and may need 64 bit or more arithmetic.

To multiply x by 1.000024 you multiply x by 24 shift right by six places and add x. Works the same in binary but with more shifts and brain strain.

You have to calculate a new envelope value for each sample otherwise you get horrible modulation effects.

RE: SystemVerilog Study Notes. FPGA ADSR envelope generator for sound synthesis (I)

dang74 — Mon, 13 Mar 2023 02:59:16 GMT

I first came across the terms attack, decay and sustain as a kid back in the 80s when I was leafing through the Commodore 64 Reference Guide that was included with my C64. Truth be told in those days it went right over my head. Thank you Javagoza. Your wonderful blog gave me a second opportunity to revisit the material and finally get a good grasp of the concepts some 35 years after the fact.

RE: SystemVerilog Study Notes. FPGA ADSR envelope generator for sound synthesis (I)

genebren — Sun, 12 Mar 2023 16:32:09 GMT

Great blog! I find this as all interesting and relevant as it tracks with my current synthesizer projects (analog/digital mix). Keep up the good work!

RE: SystemVerilog Study Notes. FPGA ADSR envelope generator for sound synthesis (I)

Jan Cumps — Sun, 12 Mar 2023 14:29:13 GMT

This is an impressive story. I have the same hardware. I'm going to try and replicate it first. Then maybe translate to VHDL
I want to improve my VHDL skills, and porting will also improve my Verilog understanding.

RE: SystemVerilog Study Notes. FPGA ADSR envelope generator for sound synthesis (I)

javagoza — Sun, 12 Mar 2023 10:03:21 GMT

I have added a zip file with the sources and other project files.