SystemVerilog Study Notes. AMD Xilinx 7 series FPGAs XADC

RE: SystemVerilog Study Notes. AMD Xilinx 7 series FPGAs XADC

zyh_buaa — Thu, 07 Nov 2024 15:13:50 GMT

May I ask if I want to read auxiliary analog inputs such as VAUXP[1]/VAUXN[1] through the XADC, should I really connect both Vp and Vn to ground? Why?

RE: SystemVerilog Study Notes. AMD Xilinx 7 series FPGAs XADC

siriusm46 — Tue, 02 Jan 2024 13:43:26 GMT

I am curious why the single-ended analog input circuit has 140 and 845 ohms? Why a bigger resistor for the ground? Is it for eliminating the analog ground noise?

RE: SystemVerilog Study Notes. AMD Xilinx 7 series FPGAs XADC

wolfgangfriedrich — Tue, 21 Mar 2023 12:14:03 GMT

I wonder if the Vivado dashboard could be utilized to visualize the XADC readings. A quick search seems to indicate yes, might be a nice option for debugging.

RE: SystemVerilog Study Notes. AMD Xilinx 7 series FPGAs XADC

ad0es — Mon, 20 Mar 2023 22:24:08 GMT

I'm a bit confused, you state:

"a sampling rate of 100M SPS (samples per second).",

but the manual says: "It is a dual 12-bit, 1 MSPS analog-to-digital converter".

RE: SystemVerilog Study Notes. AMD Xilinx 7 series FPGAs XADC

dougw — Mon, 20 Mar 2023 22:13:07 GMT

Working functionality - always a great achievenment ...