Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

guillengap — Wed, 21 Jun 2023 06:04:33 GMT

[mention:acaf6a9338de4eef8f6717d5561ed01d:e9ed411860ed4f2ba0265705b8793d05]

It's the first time I see this blog and I feel attracted to the topic because it has many applications. I want to take advantage of your knowledge in PWM signals to request your advice. I am developing a prototype with the MiniZed board to control two motors with PWM signals and using PID control.

I found a good tutorial by Adam Taylor with a simple DC motor, I repeated the experience and it works: https://www.hackster.io/adam-taylor/mini-but-mighty-the-minized-and-vitis-for-motor-control-9c376b

To generate two PWM signals, I have to make changes to the hardware (vivado) and software (vitis). My problem is that I don't know what changes have to be made because I haven't found the bibliographical references.

Adam Taylor was developing this topic with PWM signals (servos) but he only described the topic and didn't finish it: https://support.xilinx.com/s/article/744654?language=en_US

Any help or advice from you is welcome! Thank you very much in advance!

Guillermo

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

yepe — Sat, 06 May 2023 15:24:52 GMT

The project and notebook is running on my PYNQ Z1. I am measuring on PMODA channel 0, 1, 2 which must be PWM, PWMN and PULSE.

I was wondering if you know a reference manual for PYNQ to see the pinout in an intuitive way. I can see the constraints file on what output name the signals are output, but I am not sure which pins are Y17 and U18, etc. I tried measuring channel 3, 5, 6, 7 but did not see a signal. On channel 4 there seems to be a signal that starts a little earlier than PULSE and is low during the pulse train. That must be PRF, is it?

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

Jan Cumps — Fri, 05 May 2023 18:05:53 GMT

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

Jan Cumps — Fri, 05 May 2023 17:12:21 GMT

Clock signals a bit cleared out, and the domain IP split off from the ZYNQ specific config:

Content of the dark blue rectangle above:

It's not perfect. The design still has timing violations. Maybe I can spin those off to a separate blog post ...

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

yepe — Tue, 25 Apr 2023 06:46:55 GMT

Since I successfully had an output (continuous but still), I decided to test the pynq outputs with the half-bridge in just a benchtop experiment. First I added an inverter to the PWMN port (necessary for the gate driver input configuration).

Next, after generating the bitstream I can succesfully drive the half-bridge using the pynq outputs [emoticon:0f36700dfeb3494fa10d47dd9e1f90a1]

I used a +-10 V rails and it looks good so far

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

yepe — Tue, 25 Apr 2023 04:57:36 GMT

I had various issues with the project yesterday and for unknown reasons it simply could not find registers. I started over and built the project again from scratch. This time still a couple of critical errors.

But I went forward and generated the bitstream. This time no KeyErrors in the notebook! After writing a couple of commands in the notebook I tested it in the following way:

Then, probing on Y18&Y19, I see an output!

The frequency seems to be 4 MHz for some reason, but at least some progress! Very exciting stuff

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

yepe — Mon, 24 Apr 2023 09:20:34 GMT

I am following along trying to implement the design on my end. I created the following block diagram with the Pwm.vhd file from your last post

Synthesis and implementation completes, but generating the bitstream fails. Maybe I did something wrong in the block diagram or in the customization of the blocks? Or maybe I am lacking a constraint file? The internal mechanisms of the AXI interconnects are a bit of a mystery for me [emoticon:6d505171faa4497c85c5ca27290c555d]
[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:9ad5060d-3f95-472b-9afb-b73a7083771d:type=text&text=Command%3A%20write_bitstream%20-force%20Pwm.bit%0AAttempting%20to%20get%20a%20license%20for%20feature%20%27Implementation%27%20and%2For%20device%20%27xc7z020%27%0AINFO%3A%20%5BCommon%2017-349%5D%20Got%20license%20for%20feature%20%27Implementation%27%20and%2For%20device%20%27xc7z020%27%0ARunning%20DRC%20as%20a%20precondition%20to%20command%20write_bitstream%0AINFO%3A%20%5BIP_Flow%2019-234%5D%20Refreshing%20IP%20repositories%0AINFO%3A%20%5BIP_Flow%2019-1704%5D%20No%20user%20IP%20repositories%20specified%0AINFO%3A%20%5BIP_Flow%2019-2313%5D%20Loaded%20Vivado%20IP%20repository%20%27C%3A%2FXilinx%2FVivado%2F2022.2%2Fdata%2Fip%27.%0AINFO%3A%20%5BDRC%2023-27%5D%20Running%20DRC%20with%202%20threads%0AERROR%3A%20%5BDRC%20NSTD-1%5D%20Unspecified%20I%2FO%20Standard%3A%2015%20out%20of%2015%20logical%20ports%20use%20I%2FO%20standard%20%28IOSTANDARD%29%20value%20%27DEFAULT%27%2C%20instead%20of%20a%20user%20assigned%20specific%20value.%20This%20may%20cause%20I%2FO%20contention%20or%20incompatibility%20with%20the%20board%20power%20or%20connectivity%20affecting%20performance%2C%20signal%20integrity%20or%20in%20extreme%20cases%20cause%20damage%20to%20the%20device%20or%20the%20components%20to%20which%20it%20is%20connected.%20To%20correct%20this%20violation%2C%20specify%20all%20I%2FO%20standards.%20This%20design%20will%20fail%20to%20generate%20a%20bitstream%20unless%20all%20logical%20ports%20have%20a%20user%20specified%20I%2FO%20standard%20value%20defined.%20To%20allow%20bitstream%20creation%20with%20unspecified%20I%2FO%20standard%20values%20%28not%20recommended%29%2C%20use%20this%20command%3A%20set_property%20SEVERITY%20%7BWarning%7D%20%5Bget_drc_checks%20NSTD-1%5D.%20%20NOTE%3A%20When%20using%20the%20Vivado%20Runs%20infrastructure%20%28e.g.%20launch_runs%20Tcl%20command%29%2C%20add%20this%20command%20to%20a%20.tcl%20file%20and%20add%20that%20file%20as%20a%20pre-hook%20for%20write_bitstream%20step%20for%20the%20implementation%20run.%20Problem%20ports%3A%20band_i%5B3%3A0%5D%2C%20duty_i%5B5%3A0%5D%2C%20clk_i%2C%20enable_i%2C%20n_reset_i%2C%20pwmA_o%2C%20and%20pwmB_o.%0AERROR%3A%20%5BDRC%20UCIO-1%5D%20Unconstrained%20Logical%20Port%3A%2015%20out%20of%2015%20logical%20ports%20have%20no%20user%20assigned%20specific%20location%20constraint%20%28LOC%29.%20This%20may%20cause%20I%2FO%20contention%20or%20incompatibility%20with%20the%20board%20power%20or%20connectivity%20affecting%20performance%2C%20signal%20integrity%20or%20in%20extreme%20cases%20cause%20damage%20to%20the%20device%20or%20the%20components%20to%20which%20it%20is%20connected.%20To%20correct%20this%20violation%2C%20specify%20all%20pin%20locations.%20This%20design%20will%20fail%20to%20generate%20a%20bitstream%20unless%20all%20logical%20ports%20have%20a%20user%20specified%20site%20LOC%20constraint%20defined.%20%20To%20allow%20bitstream%20creation%20with%20unspecified%20pin%20locations%20%28not%20recommended%29%2C%20use%20this%20command%3A%20set_property%20SEVERITY%20%7BWarning%7D%20%5Bget_drc_checks%20UCIO-1%5D.%20%20NOTE%3A%20When%20using%20the%20Vivado%20Runs%20infrastructure%20%28e.g.%20launch_runs%20Tcl%20command%29%2C%20add%20this%20command%20to%20a%20.tcl%20file%20and%20add%20that%20file%20as%20a%20pre-hook%20for%20write_bitstream%20step%20for%20the%20implementation%20run.%20%20Problem%20ports%3A%20band_i%5B3%3A0%5D%2C%20duty_i%5B5%3A0%5D%2C%20clk_i%2C%20enable_i%2C%20n_reset_i%2C%20pwmA_o%2C%20and%20pwmB_o.%0AWARNING%3A%20%5BDRC%20ZPS7-1%5D%20PS7%20block%20required%3A%20The%20PS7%20cell%20must%20be%20used%20in%20this%20Zynq%20design%20in%20order%20to%20enable%20correct%20default%20configuration.%0AINFO%3A%20%5BVivado%2012-3199%5D%20DRC%20finished%20with%202%20Errors%2C%201%20Warnings%0AINFO%3A%20%5BVivado%2012-3200%5D%20Please%20refer%20to%20the%20DRC%20report%20%28report_drc%29%20for%20more%20information.%0AERROR%3A%20%5BVivado%2012-1345%5D%20Error%28s%29%20found%20during%20DRC.%20Bitgen%20not%20run.%0AINFO%3A%20%5BCommon%2017-83%5D%20Releasing%20license%3A%20Implementation%0A15%20Infos%2C%201%20Warnings%2C%200%20Critical%20Warnings%20and%203%20Errors%20encountered.%0Awrite_bitstream%20failed%0AERROR%3A%20%5BCommon%2017-39%5D%20%27write_bitstream%27%20failed%20due%20to%20earlier%20errors.]

Looking at the log, it seems to be related to IO

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

Jan Cumps — Sun, 23 Apr 2023 10:19:32 GMT

A capture with a little logic analyser (that runs on a Spartan 6).

You see the PWM and PWMN, with 3 clocks of dead band. And the PULSE signal

Begin

Tail

Looks like PULSE falls a little too early?

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

Jan Cumps — Sat, 22 Apr 2023 22:35:53 GMT

test of using a control block, that generates a PULSE signal and controls the pulse train: