Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

yepe — Mon, 08 May 2023 12:06:27 GMT

Is my understanding accurate that the maximum gate delay is determined by the register size and master clock period?

I have tried setting the gate delay in the notebook to larger values but it seems to time the same as:

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

yepe — Sun, 07 May 2023 10:03:09 GMT

Amazing, is it possible you could make a zip of the version in this post?

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

Jan Cumps — Sun, 07 May 2023 08:00:29 GMT

The additional 20 MHz demodulation clock:

The clock is not guaranteed in phase with the PWM. If that's a requirement, the state changes of the signal controller would have to be synced with the 20 MHz clock.
Not impossible, but a bit involved because the PWM module takes a clock tick to start up [emoticon:c4563cd7d5574777a71c318021cbbcc8]

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

dang74 — Sun, 07 May 2023 00:08:18 GMT

Good post. It reminds me that I have to try and find my Arty board.

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

scottiebabe — Sat, 06 May 2023 20:08:22 GMT

Scope GIF! [emoticon:9b06bfad0e6a482e801e5eb8fd9025d6]

RE: Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

DAB — Sat, 06 May 2023 20:08:22 GMT

Nice post Jan.