The Art of FPGA Design - Post 40

The Art of FPGA Design - Post 40/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-40Instantiating the DSPFP32 the Easy Way The final thing we need to use the new Versal DSPFP32 hardened floating point primitive is a way to access them through VHDL code. While it would be very nice to be able to infer the primitives, especially sinceen-USTelligent Community 12RE: The Art of FPGA Design - Post 40https://community.element14.com/technologies/fpga-group/b/blog/posts/the-art-of-fpga-design---post-40Tue, 23 Jan 2024 23:43:34 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:75633eaa-ac15-4ae8-983c-38f3c322c193LenSDR0<p>HI fpgaguru,</p> <p>Nice to see you're still posting!!!  </p> <p>This is great stuff!! </p> <p>Any chance of getting the accompanying rtl, either VHDL or System Verilog, to your posts in "The Art of FPGA Design Season 2 - Digital Signal Processing" section??</p> <p>Regards,</p> <p>Len</p><img src="https://community.element14.com/aggbug?PostID=27371&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">