RE: Software Defined Transceiver Redux

flyingbean — Tue, 27 Feb 2024 20:44:35 GMT

I don't know how many DSP tiles you would need for the SDR math on a signal FPGA. 4 Transceivers on Kintex 7 can offer you a lot of options for baseband applications. Looking forward to reading your blogs on this topic in 2024.

RE: Software Defined Transceiver Redux

shabaz — Mon, 26 Feb 2024 22:13:41 GMT

Hi, just curious, what's the application?

With such a large bandwidth (the entire HF band it seems?) isn't there almost a guarantee that the front end ADC will suffer from overload from segments of the spectrum?

It would be far cheaper to (say) split the spectrum into several (for instance three) chunks, so that each one fits into USB-C bandwidth, and even if there's concern there could be bits missing in the overlaps, extra in-between chunks (e.g. two chunks in this example) could overlap those three chunks. The idea being that the processing for each spectrum chunk would be done with a separate processor (e.g. normal processor, or perhaps GPU), and the sum of them may be cheaper than the $3K for the FPGA board, plus there's the significant benefit of pre-ADC filtering per spectrum chunk.

There's no protocol over HF that can possibly cover a such a large bandwidth (even with frequency-hopping), so only one processor would ever need to process the data for any single data stream, if the problem was split this way into spectrum chunks.