Mini Project for learning HDL/Verilog: Making a part of a very small processor/technologies/fpga-group/b/blog/posts/mini-project-for-learning-hdl-verilog-making-a-part-of-a-very-small-processorHii all, This is me first time posting here on element14. I recently completed a Hardware Description of a part of a processor in Verilog. In this mini project, I ensured the datapaths, added 7 registers ( 6 normal and 1 special). The special registeen-USTelligent Community 12RE: Mini Project for learning HDL/Verilog: Making a part of a very small processorhttps://community.element14.com/technologies/fpga-group/b/blog/posts/mini-project-for-learning-hdl-verilog-making-a-part-of-a-very-small-processorTue, 08 Apr 2025 20:14:35 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:4276638b-5e70-4b4e-9cfa-9ecaffedb7f6DAB1<p>Nice start.</p><img src="https://community.element14.com/aggbug?PostID=28818&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">RE: Mini Project for learning HDL/Verilog: Making a part of a very small processorhttps://community.element14.com/technologies/fpga-group/b/blog/posts/mini-project-for-learning-hdl-verilog-making-a-part-of-a-very-small-processorMon, 07 Apr 2025 15:17:41 GMT93d5dcb4-84c2-446f-b2cb-99731719e767:4276638b-5e70-4b4e-9cfa-9ecaffedb7f6michaelkellett2<p>Have you thought about drawing&nbsp; a block diagram of your design ?</p> <p>Or maybe letting the tools draw a diagram for you.</p> <p>It is very difficult to read through Verilog (or VHDL) and work out the intent.</p> <p>I find that designing at the block diagram level makes it much easier and gives better results.</p> <p>(Even if the diagram is just a drawing and not translated into an HDL automatically).</p> <p>MK</p><img src="https://community.element14.com/aggbug?PostID=28818&AppID=19&AppType=Weblog&ContentType=0" width="1" height="1">