/technologies/fpga-group/b/blog/posts/bringing-up-an-ad9361-class-2t2r-transceiver-on-zynq-7000-part-1-clock-plan-data-interface-and-the-first-linkI'm starting a project log for a wideband 2T2R RF front end built around an AD9361-class transceiver paired with a Zynq-7000 (the same class of platform many SDR boards use). The goal is a working, documented bring-up: stable clocking, a reliable...en-USTelligent Community 12