Entering The World Of FPGA's with a DEO-NANO P0082 - Part 5 (modelling a M74HC590)

RE: Entering The World Of FPGA's with a DEO-NANO P0082 - Part 5 (modelling a M74HC590)

jw0752 — Sat, 26 Aug 2017 05:53:46 GMT

Hi Lucie,

I enjoyed your presentation. Reading through the discussion afterwards reminded me what it was like as a child to sit and listen to the grown-ups talk. I understood just enough to be really impressed with everyone.

John

RE: Entering The World Of FPGA's with a DEO-NANO P0082 - Part 5 (modelling a M74HC590)

DAB — Fri, 25 Aug 2017 19:39:51 GMT

Good post Lucie.

Your compile results helped to provide me with a gage on just how many devices you might be able to setup in this FPGA.

You are definitely answering the basic question I had about the product.

Well done.

DAB

RE: Entering The World Of FPGA's with a DEO-NANO P0082 - Part 5 (modelling a M74HC590)

rachaelp — Fri, 25 Aug 2017 18:41:49 GMT

As [mention:fbb6a29175924ef2b9847498e58a0842:e9ed411860ed4f2ba0265705b8793d05] gave you his implementation of your design in Verilog, I've gone ahead and thrown something similar together in VHDL. I've not run it through a compiler or checked syntax and it's off the top of my head so I might have got something wrong as I am a tad rusty but here goes:

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:3ef06e6b-9b7d-4651-b12d-db8be7f5e991:type=text&text=library+IEEE%3B%0Ause+IEEE.std_logic_1164.all%3B%0Ause+IEEE.numeric_std.all%3B%0A%0Aentity+74HC590+is%0Abegin%0A+++port+%28%0A++++++CCK+++%3A+in++std_logic%3B++++++++++++++++++++%2F%2F+Counter+clock%2C+rising+edge.%0A++++++CCKEN+%3A+in++std_logic%3B++++++++++++++++++++%2F%2F+Counter+clock+enable%2C+active+LOW.%0A++++++RCK+++%3A+in++std_logic%3B++++++++++++++++++++%2F%2F+Register+clock%2C+rising+edge.%0A++++++G+++++%3A+in++std_logic%3B++++++++++++++++++++%2F%2F+Output+enable%2C+active+LOW.%0A++++++CCLR++%3A+in++std_logic%3B++++++++++++++++++++%2F%2F+Counter+clear%2C+active+LOW.%0A++++++RCO+++%3A+out+std_logic%3B++++++++++++++++++++%2F%2F+Ripple+carry+output%2C+active+low.%0A++++++Q+++++%3A+out+std_logic_vector+%287+downto+0%29+%2F%2F+Chip+output%2C+may+be+high-Z.%0A+++%29%0Aend+entity%3B%0A%0Aarchitecture+RTL+of+74HC590+is%0A%0Asignal+countVal+%3A+std_logic_vector+%287+downto+0%29%3B%0Asignal+RCO_i++++%3A+std_logic%3B%0Asignal+CCK_last+%3A+std_logic%3B%0A%0Abegin%0A%0A--+Counter+process%0ACOUNT1%3A+process+%28RCK%29+--+Only+RCK+needs+to+be+in+the+sensitivity+list+as+the+process+is+fully+synchronous.%0Abegin%0A+++if+rising_edge+%28RCK%29+then%0A++++++countVal+%3C%3D+countVal%3B%0A++++++CCK_last+%3C%3D+CCK%3B%0A++++++if+%28CCLR+%3D+%270%27%29+then%0A+++++++++countVal+%3C%3D+X%2200%22%3B%0A++++++elsif+%28CCKEN+%3D+%270%27%29+then%0A+++++++++if+%28CCK+%3D+%271%27+and+CCK_last+%3D+%270%27%29+then%0A++++++++++++if+%28countVal+%3E%3D+X%22FF%22%29+then%0A+++++++++++++++countVal+%3C%3D+X%2200%22%3B%0A++++++++++++else%0A+++++++++++++++countVal+%3C%3D+countVal+%2B+X%2201%22%3B%0A++++++++++++end+if%3B%0A+++++++++end+if%3B%0A++++++end+if%3B%0A+++end+if%3B%0Aend+process%3B%0A%0ARCO_i+%3C%3D+%270%27+when+countVal+%3D+X%22FF%22+else+%271%27%3B%0A%0A--+Assign+to+outputs+and+create+the+tristate+buffers%0AQ+%3C%3D+countVal+when+G+%3D+%271%27+else+%28others+%3D%3E+%27Z%27%29%3B%0ARCO+%3C%3D+RCO_i+when+G+%3D+%271%27+else+%27Z%27%3B%0A%0Aend+architecture%3B]

It's also possible to have an asynchronous reset but as [mention:a5312e9762dd4699ba5d3876da34ffe5:e9ed411860ed4f2ba0265705b8793d05] pointed out, you don't necessarily want to have asynchronous things going on in your FPGA. A global reset can be ok but again you need to be careful to ensure at startup your entire chip comes out of reset at the same time.

Best Regards,

Rachael

RE: Entering The World Of FPGA's with a DEO-NANO P0082 - Part 5 (modelling a M74HC590)

johnbeetem — Fri, 25 Aug 2017 17:54:04 GMT

If you're interested, here's how I'd write the Verilog for the 74HC590. Along with your data sheet excerpts I downloaded a data sheet from Nexperia, the new name for Philips' jellybean semiconductors, originally Signetics (yep, I'm old).

// The I/Os are pretty much the same except that RCO is not registered: it's combinational and only depends on the current value of the counter. I've also made a separate output port Q since it may be high-impedance. I've named the internal counter register "K" and storage register "R" to save typing.

input CCK; // Counter clock, rising edge.

input CCKEN; // Counter clock enable, active LOW.

input RCK; // Register clock, rising edge.

input G; // Output enable, active LOW.

input CCLR; // Counter clear, active LOW.

output RCO; // Ripple carry output, active low.

output [7:0] Q; // Chip output, may be high-Z.

reg [7:0] K; // Counter register.

reg [7:0] R; // Storage register.

// Updating R from K is unconditional.

always @(posedge RCK) begin R <= K; end

// This is compacted from your version by making CCKEN a carry-in.

always @(posedge CCK or negedge CCLR)

begin

if (!CCLR) K <= 0; else K <= K + !CCKEN;

end

// Q is high-impedance if OE is high and outputs the storage register R if OE is active low.

assign Q = OE? 8'hzz: R;

// The RCO output only depends on the current value of K. It's not clocked.

assign RCO = K != 255; // RCO is low when K = 255.

RE: Entering The World Of FPGA's with a DEO-NANO P0082 - Part 5 (modelling a M74HC590)

michaelkellett — Fri, 25 Aug 2017 08:43:44 GMT

Hello Lucie,

I don't think this will work properly

always @ (posedge CCK or negedge CCLR)

It's legal Verilog but:

It wont' work like the chip because CCLR is an asynchronous reset in real life. In fact I'm not sure what it will do because the FPGA doesn't have edge detect hardware - the construction always @ (posedge CCK) gives the synthesizer a hint that you want to make a synchronous process using CCK as the clock so it connects CCK to the clock port of its flip-flops. The hardware has no way of ORing the edges so the synthesizer will make some assumptions (didn't it give a warning ?).

I don't use Verilog because I think it is more susceptible to this kind of problem.

There is some more explanation here:

https://electronics.stackexchange.com/questions/26502/verilog-check-for-two-negedges-in-always-block

In real life it is almost never a good idea to do FPGA design based on emulation of standard logic chips.

Even having an asynchronous clear for a counter on an FPGA is bad news - the usual way is to synchronize the clear and reset signals to the clock - but that wouldn't be like the chip either.

The problem is that if the CCLR and CCK edges get too close together in time the design won't meet the timing constraints of the chip and won't behave predictably - the only way to design with FPGAs and have the tools make good predictions about timing margins is to design synchronously.