<?xml-stylesheet type="text/xsl" href="https://community.element14.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>XXICC (21st Century Co-design) release 0.0r</title><link>/technologies/fpga-group/b/blog/posts/xxicc-21st-century-co-design-release-0-0r</link><description>Here is the new release 0.0r of XXICC. I&amp;#39;ve been horrifically busy with work and family obligations over the last two years so I wasn&amp;#39;t able to keep up with XXICC. Also, 0.0r is a major release since it adds integer nets and opera...</description><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: XXICC (21st Century Co-design) release 0.0r</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/xxicc-21st-century-co-design-release-0-0r</link><pubDate>Sun, 26 Aug 2018 11:45:50 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:f84a9687-497f-4289-b6b4-2357241655ba</guid><dc:creator>groventov</dc:creator><slash:comments>1</slash:comments><description>&lt;p&gt;What happend to this marvelous project. No activity since one year ago!!! &lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=3473&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: XXICC (21st Century Co-design) release 0.0r</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/xxicc-21st-century-co-design-release-0-0r</link><pubDate>Sun, 26 Aug 2018 10:44:47 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:f84a9687-497f-4289-b6b4-2357241655ba</guid><dc:creator>groventov</dc:creator><slash:comments>0</slash:comments><description>&lt;p&gt;No activity for more than one year. What happened to XXICC?&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=3473&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item><item><title>RE: XXICC (21st Century Co-design) release 0.0r</title><link>https://community.element14.com/technologies/fpga-group/b/blog/posts/xxicc-21st-century-co-design-release-0-0r</link><pubDate>Thu, 24 Aug 2017 22:23:04 GMT</pubDate><guid isPermaLink="false">93d5dcb4-84c2-446f-b2cb-99731719e767:f84a9687-497f-4289-b6b4-2357241655ba</guid><dc:creator>e14 Contributor</dc:creator><slash:comments>2</slash:comments><description>&lt;p&gt;Its definitely a good idea to produce a language/compiler which feels more comfortable to work with. My recent escapades in Verilog proves so, as a basic example I was using multiple [always @] blocks to perform seperate tasks but later found out that wire/reg types could only be modified in 1[always @]block. This led me to re-writing the entire thing to work around the compilers constraints.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Its only a small issue and I&amp;#39;ve learnt for the future but a more intelligent compiler would be able to compile my original by automatically combining what I&amp;#39;d written into a single block itself.&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Its clear that your software here is going way above and beyond that but it does seem there&amp;#39;s a lot of improvements that could and should be made merely as a matter of language/compiler evolution.&lt;/p&gt;&lt;img src="https://community.element14.com/aggbug?PostID=3473&amp;AppID=19&amp;AppType=Weblog&amp;ContentType=0" width="1" height="1"&gt;</description></item></channel></rss>