Gnarly Grey UPduino

RE: Gnarly Grey UPduino

prbhkrkmr — Mon, 20 Jan 2020 09:01:21 GMT

Hi,

I saw a Xilinx Vivado Tutorial basic flow 1 about a Johnson Counter implementation that dissipates 8 watts of power!

I have cross verified with ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1). Still the counter implemetation dissipated 2 watts power.

Is this usual..?

Regards

RE: Gnarly Grey UPduino

clem57 — Mon, 20 Jan 2020 07:36:35 GMT

According to https://pingu98.wordpress.com/2019/04/08/how-to-build-your-own-cpu-from-scratch-inside-an-fpga/ , a RISC V processor can be built on a FPGA. Will this work on this board? How about a miniZed from Avnet? [mention:a5312e9762dd4699ba5d3876da34ffe5:e9ed411860ed4f2ba0265705b8793d05]

RE: Gnarly Grey UPduino

prbhkrkmr — Mon, 20 Jan 2020 04:56:57 GMT

Hi,

I had a quick look at the PCB files and have a query. Is there a keep-out layer for the PCB?

Regards

RE: Gnarly Grey UPduino

vr2045 — Mon, 23 Dec 2019 02:03:03 GMT

Hello folks,

Happy to report that the layout for the UPduino 3.0 is now complete and the design is uploaded on GitHub. This incorporates all the feedback I received and is summarized in the wiki page here. I created a blog that documents my analysis related to the PLL issue here.

Thank you!

RE: Gnarly Grey UPduino

vr2045 — Mon, 16 Sep 2019 20:13:12 GMT

Hello folks,

I’ve taken over the production of the UPduino’s from Lattice recently (GitHub site is here) and would love to hear your feedback. WIll be sold on Tindie soon. I created a Survey for this but would also love to hear feedback from the community on how to make this a better platform.

Thank you,

RE: Gnarly Grey UPduino

aventuri — Tue, 27 Feb 2018 09:48:49 GMT

hi,

just a note about a new software called Lattice Radiant that has been released.

it should target precisely the Upduino FPGA iCE40 UltraPlus UP5K.. it should run both on Windows and Linux. But a quick shot to install it on Debian turned me down, because it says "Fedora/RedHat" only.. let's see in next days..

there's also a tool "Reveal Analyzer" as an In-circuit debugger module.. let's see if it's helpful/useful also for custom boards..

I'm really wondering why they departed from IceCube2 with a new IDE specifically for UltraPlus.. anyone hints?

bye

andrea

RE: Gnarly Grey UPduino

aventuri — Wed, 24 Jan 2018 05:24:32 GMT

hello, just a few notes about advancement on UP5K support and a test firmware.

since a few days the "official" FPGA opensource toolchain (yosys, arachne-pnr & icestorm) supports (fairly completely) the UP5K part.

then, i've just made a (pretty simple) extension of a RISCV-32 ice40 port (original repo is icicle) for UP5K; the github repo is: https://github.com/aventuri/icicle

with make upduino you'll get a firmware to upload to upduino board and see on the serial port the helloWorld greeting! the pins are:

21 is uartTx,
12 is uartRX,

of course you need a working risc-v gcc toolchain and an USB-TTL adapter, if you do not already have just a cable on a UART TTL pins of an SBC

[View:/resized-image/__size/341x155/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-bcb74514-4743-4d75-89e1-546a02174692/contentimage_5F00_185357.jpg:341:155]

BTW i had to add three (3) 1uF 0603 decoupling CAPS for PLL stability as per this post!! two on the front as per the picture above. one one the back, on the same pins of the other LDO.

RE: Gnarly Grey UPduino

peepo — Sun, 24 Dec 2017 16:18:06 GMT

PLL: the UPDuino has the series 100R resistor but does not have a capacitor on the FPGA side of the resistor to ground.

Buy that man a drink!!!

RE: Gnarly Grey UPduino

peepo — Fri, 22 Dec 2017 19:18:22 GMT

[View:/resized-image/__size/620x496/__key/commentfiles/f7d226abd59f475c9d224a79e3f0ec07-bcb74514-4743-4d75-89e1-546a02174692/5023.contentimage_5F00_185356.jpg:620:496]

RE: Gnarly Grey UPduino

peepo — Fri, 22 Dec 2017 18:01:17 GMT

re-soldered 8x pins on flash, pin 5 aka DQ0 lifted away from board, wfm.

RE: Gnarly Grey UPduino

peepo — Fri, 22 Dec 2017 14:57:40 GMT

Comments and Suggestions sought,

When using iCEprog with Adafruit FT232H to upload an .bin to UPduino:

...

programming..

reading..

Found difference between flash and file!

ABORT.

seems to be intermittent fault, and wastes a lot of time.

using iceprog -v

...

waiting..

reading..

read 0x000000 +0x100

ff ff ff ff ...

RE: Gnarly Grey UPduino

aventuri — Mon, 27 Nov 2017 23:13:07 GMT

Hello, just a quick update to point out where you can find a mostly working open source toolchain supporting the UP5K!

https://github.com/daveshah1/icestorm/tree/up5k_ip

https://github.com/daveshah1/arachne-pnr/tree/up5k

https://github.com/daveshah1/yosys/tree/up5k

with these three branches, you can create bitstreams for the Upduino board!

amazing..

thanx to David Shah for the commitment!

RE: Gnarly Grey UPduino

peepo — Sun, 05 Nov 2017 13:07:14 GMT

Grant, are you able to offer a with extra chip(s) option?

ie buy an UPDuino and get some extra UP5K chips, at a price...

RE: Gnarly Grey UPduino

johnbeetem — Wed, 04 Oct 2017 02:56:02 GMT

IceStorm development for the iCE40 UP5K is happening!

https://github.com/cliffordwolf/icestorm/issues/68

RE: Gnarly Grey UPduino

aventuri — Tue, 03 Oct 2017 23:30:40 GMT

let me start saying the review is a bit too hard IMHO; i believe that the ratio performance/price is still huge..

the FPGA is good and community will surely help in doing content, porting design and documentation. maybe we'll see how critical are the EMI on high speed design, eventually. THE blinking led is always working!

i have anyway a little gem to share about the provisioning of the parts of this board. is something that amazed me really..

the story begins when i've finally put together a small program for uploading bitstream on both FPGA SRAM and FLASH from an Allwinner SOC (A10/A20). you can find it here..

Icoprog, the application i borrowed the overall skeleton [*] had also the feature to read back the FLASH content, so i decided to dump the content, before doing any writing..

you can't imagine how i was amazed to see lot's of strings already present inside the flash. i supposed it could be filled with a sample bitstream (the notorius blinking led.. but it wasn't blinking if closing the jumper between iCE Chip select and Flash CS)

no, the strings are saying another story!! here a small glimpse:

...

bcm56334_a0_bmd_port_mode_set[%d]: drain failed on port %d

chip/bcm56334_a0/bcm56334_a0_bmd_port_stp_get.c

bcm56334_a0_xport_reset[%d]: TX PLL did not lock on port %d

bcm56334_miim_int

bcm956334k28_miim_ext

bcmi_nextgen65_serdes

Internal 65nm NextGen 1.25G SerDes PHY Driver

bcmi_unicore16g_xgxs

Internal Unicore 16G XGXS PHY Driver

Available commands:

Summary of commands:

NX9-loader-01.56

...

and at the end, a SNMP string telling the whole story:

CN=CiscoSystems;OU=Nexus9k;O=CiscoSystems

this is the flash of a CISCO switch!! ..used parts.. can't believe.. who's selling refurbished stuff? China low costs assemblers? what savings?

really amazing

andrea

[*] it's borrowed from icoprog, that's the same for Raspberry (me i'm not a Raspi fan, anyway..) so i swapped the underlying library from WiringPI and put direct access with memory map of pins of Allwinner.. a bit rough but effective..