/technologies/fpga-group/b/blog/posts/minized-ddr-delay-values-in-vivado-block-designQuestion: How did Avnet arrive at the DDR Delay values published in the MiniZed board definition file? That's a good question! We developed the MiniZed board definition file with Vivado 2016.4. The settings you will find in the Avnet MiniZed boa...en-USTelligent Community 12